Sense amplifier for a dynamic RAM

Details Sense amplifier for a dynamic RAM Sense amplifier for a dynamic RAM

1982-12-30

1987-05-26

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365210, 365149, 365203, G11C 700

Patent

active

046690638

ABSTRACT:
A single ended sense amplifier (10) receives a bit line signal (16) at the gate of a detector MOS transistor (36). The source of the detector transistor (36) is connected to a reference voltage (24) which is adjusted prior to each memory cycle to make the gate to source voltage of the detector transistor (36) equal to the approximate threshold voltage of the transistor. The drain of the detector transistor (36) gates an amplifier transistor (30) which inhibits or passes a read signal (18) to the gate of a digit line pull down transistor (32) which provides an active pull down on a digit line (26) that is precharged to a high voltage prior to a memory read cycle.

REFERENCES:
patent: 3789312 (1974-01-01), Heller et al.
patent: 3983545 (1976-09-01), Cordaro
patent: 4003034 (1977-01-01), Au
patent: 4057789 (1977-11-01), Spadavecchia et al.
patent: 4270190 (1981-05-01), Jindra et al.
patent: 4414547 (1983-11-01), Knapp et al.
patent: 4449203 (1984-05-01), Adlhoch
patent: 4460985 (1984-07-01), Hoffman

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