Sense amplifier control circuit in semiconductor memory

Details Sense amplifier control circuit in semiconductor memory Sense amplifier control circuit in semiconductor memory

1999-10-21

2000-08-15

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Differential sensing

365205, 365194, G11C 702, G11C 700

Patent

active

061046566

ABSTRACT:
A sense amplifier control circuit in a semiconductor memory supplies a sense amplifier with two power source voltages with voltage levels different from each other, successively. A first logic gate is supplied with a pair of sense amplifier enabling bar signals which are applied to the first logic gate in order. The first logic gate generates a signal of logic value 0 when at least one of the sense amplifier enabling bar signals has logic value 1. A second logic gate generates a first NMOS sense amplifier enabling bar signal of high level when an output of the first logic gate has logic value 0 and a sense amplifier enabling bar signal has logic value 1. A third logic gate generates a first PMOS sense amplifier enabling bar signal of high level when at least one of an output of the first logic gate and a sense amplifier enabling bar signal has logic value 1. A fourth logic gate generates a signal of logic value 1 when at least one of a plurality of MAT selection bar signals has logic value 0. A fifth logic gate generates a signal of logic value 1 when the first NMOS sense amplifier enabling bar signal has logic value 0 and an output of the fourth logic gate has logic value 1. A sixth logic gate generates a signal of logic value 0 when the first PMOS sense amplifier enabling bar signal has logic value 1 and an output of the fourth logic gate has logic value 0, and a seventh logic gate generates a second PMOS sense amplifier control signal of logic value 1 when the outputs of the fifth and sixth logic gates both have logic value 1.

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