Sense amplifier circuit for use in a semiconductor memory...

Details Sense amplifier circuit for use in a semiconductor memory... Sense amplifier circuit for use in a semiconductor memory...

2000-09-27

2002-04-30

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S190000, C365S210130

Reexamination Certificate

active

06381187

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority from Korean Priority Document No. 99-41976, filed on Sep. 30, 1999 with the Korean Industrial Property Office, which document is hereby incorporated by reference.
FIELD OF THE INVENTION
The present invention relates to semiconductor integrated circuit devices, and more particularly to a sense amplifier circuit of a semiconductor memory device.
BACKGROUND OF THE INVENTION
A conventional sense amplifier circuit used by a semiconductor memory device is illustrated in FIG.
1
. The memory device includes a data line DL connected to a power supply voltage through a PMOS transistor MP
2
, an NMOS transistor MN
2
which is switched by a column select signal Ysel, and a bit line BL connected to the data line DL through the NMOS transistor MN
2
. Between the bit line BL and the ground, only one memory cell transistor MC is depicted. However, it is obvious to ones skilled in the art that more memory cell transistors (not shown) can be connected therebetween.
The conventional sense amplifier includes a current mirror type differential amplifier
10
, and a dummy data line DDL symmetrical to the data line DL. The dummy data line DDL is connected to a power supply voltage through a PMOS transistor MP
1
. It includes an on-state NMOS transistor MN
1
, a dummy bit line DBL coupled to the dummy data line DDL through an NMOS transistor MN
1
, and a dummy memory cell, which consists of dummy memory cell transistors DMC
1
and DMC
2
connected in series between the dummy bit line DBL and a ground. Herein, the NMOS transistor MN
1
is used to provide the same RC loading as the NMOS transistor MN
2
switched by the column select signal Ysel.
The PMOS transistors MP
1
and MP
2
constitute a current mirror so as to supply the data line DL and the dummy data line DDL with the same amount current to one another. An input IN
1
of the differential amplifier
10
is coupled to the dummy data line DDL, and the other input IN
2
thereof is coupled to the data line DL. The differential amplifier
10
detects a voltage difference between the data line DL and the dummy data line DDL to output a signal Sout of a logic low level or a logic high level as a detection result.
In
FIG. 1
, each dummy memory cell transistors DMC
1
and DMC
2
has the same size and characteristic as the on-state memory cell transistor MC, respectively. According to this structure, a current which flows through the dummy memory cell transistors DMC
1
and DMC
2
(hereinafter, referred to as a dummy cell current) corresponds to one-half of a current which flows through the on-state memory cell transistor MC (hereinafter, referred to as an on cell current). That is, the dummy cell current has an intermediate value of the on and off cell currents. Herein, if a current (hereinafter, referred to as an off cell current) flowing via an off-state memory cell MC is ideally ‘0’, the dummy cell current corresponds to one-half of the on cell current. A diagram showing an ideal relationship between the on cell current, the off cell current, and the dummy cell current is illustrated in FIG.
2
.
It can be seen in
FIG. 2
that the dummy cell current is increased following the intermediate value of both the on cell current and the off cell current as the power supply voltage is increased. In a sense amplifier circuit designed according to such a current characteristic, a voltage of the dummy data line DDL corresponds to an intermediate voltage between a first voltage and a second voltage. The first voltage is a voltage induced on the data line DL when a memory cell MC is at the on state, and the second voltage is a voltage induced on the data line DL when the memory cell MC is at the off state. Therefore, a satisfactory sensing margin for the on-state memory cell transistor and the off-state memory cell transistor can be sufficiently secured.
In the conventional sense amplifier circuit, the dummy cell current which has the intermediate value of the on cell current (when the off cell current is ‘0’) is obtained by connecting two dummy memory cell transistors in series, which have the same characteristic and size as the on-state memory cell transistor, respectively. But, it has proven very difficult to attain the theoretical ideal of FIG.
2
. This is because generally, a current flowing via the memory cell transistor MC is a current which is obtained passing various elements such as a string select transistor, RC loading, or the like. The problem has been that the characteristics of the various elements can vary due to a number of factors, such as variations in processing, a different operating voltage, or a different operating temperature. This makes the dummy cell current be set less or more than the intermediate value of the on cell current, which generates a reduced on cell margin and off cell margin.
A frequent result is seen in FIG.
3
. The dummy cell current is not in the middle of the on cell current and the off cell current curves. At some extreme values of small voltage, the dummy cell current isn't even between the curves. Accordingly, in the sense amplifier circuit scheme which generates the dummy cell current by using two serially-connected dummy memory cell transistors, the sensing margin for either the off-state memory cell transistor or the on-state memory cell transistor is reduced from what is illustrated in FIG.
2
. And, in some extreme cases, it vanishes. Indeed, the dummy cell current can be even higher than the on cell current. That is, the voltage of the dummy data line DDL can be lower than the voltage of the data line DL when the memory cell is at the on state, or can be higher than the voltage of the data line DL when the memory cell is at the off state.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a sense amplifier circuit capable of securing a stable on/off cell sensing margin.
It is another object of the invention to provide a sense amplifier circuit with a double load structure capable of easily obtaining a current which has an intermediate value between an on cell current and an off cell current.
In order to attain the above objects, according to an aspect of the present invention, there is provided a sense amplifier circuit for discriminating an on/off state of a memory cell transistor. The sense amplifier circuit comprises a data line, a dummy data line, first through third load transistors, and a differential amplifier. The data line is connected to the memory cell transistor, and the dummy data line is connected to a dummy memory cell transistor. The first and second load transistors are used for driving the dummy data line from the power supply voltage. Coupled as a current mirror, the third load transistor drives the data line from the power supply voltage at half the current, resulting from the 2:1 ratio of the current mirror. The differential amplifier receives signals from the data line and the dummy data lines, and then outputs either a logic low level or a logic high level according to a state of the memory cell transistor.


REFERENCES:
patent: 5142495 (1992-08-01), Canepa
patent: 5355333 (1994-10-01), Pascucci
patent: 5381374 (1995-01-01), Shiraishi et al.
patent: 5627790 (1997-05-01), Golla et al.

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