Sense amplifier block layout for use in a dynamic random access

Details Sense amplifier block layout for use in a dynamic random access Sense amplifier block layout for use in a dynamic random access

1999-05-17

2000-04-04

Nelms, David

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365203, G11C 700

Patent

active

060469501

ABSTRACT:
A semiconductor memory device of the present invention comprises at least two memory cell blocks having a plurality of bit line pairs, respectively, and a plurality of sense amplifier blocks arranged between the memory cell blocks. Each sense amplifier block has two bit line precharge transistors, one equalization, and two bit line isolation transistors. The device further comprises an unit precharge-isolation region which has a) an width in which two bit line pairs are disposed, wherein the transistors are fabricated in the unit precharge-isolation region, b) two active regions arranged in the unit precharge-isolation region, wherein the precharge and equalization transistors are placed in the other of the active regions, and c) five active to bit line contacts arranged in zigzag within the active regions. According to the structure of the present invention, three gate electrodes of the transistors are disposed at the corresponding active regions in "h-l-l" shape.

REFERENCES:
patent: 5701268 (1997-12-01), Lee et al.

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