Sense amplifier and or gate for a high density programmable logi

Details Sense amplifier and or gate for a high density programmable logi Sense amplifier and or gate for a high density programmable logi

1994-11-17

1996-10-22

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 44, 327 51, H03K 19173

Patent

active

055680666

ABSTRACT:
A high density programmable logic device (PLD) having sense amplifiers and OR gates configured to increase operation speed and reduce transistor count from previous circuits as well as to provide a selectable power down mode on a macrocell-by-macrocell basis. The sense amplifiers include a single cascode in the data path connecting a product term to the OR gates. The OR gates utilize a plurality of source follower transistors followed by pass gates to provide logic allocation enabling the sense amplifier outputs to be reduced from the 0.0 V-5.0 V CMOS rails to increase switching speed while reducing overall transistor count. Amplifying inverters normally provided in the sense amplifiers to provide the CMOS rail-to-rail switching and which would require complex feedback for providing power down on a macrocell-by-macrocell basis are moved forward into OR output circuits. Power down on a macrocell-by-macrocell basis is provided by selectively sizing the amplifying inverters in the OR output circuits.

REFERENCES:
patent: 4758746 (1988-07-01), Birkner
patent: 4769562 (1988-09-01), Ghisio
patent: 4839539 (1989-06-01), Takata et al.
patent: 4899070 (1990-02-01), Ou et al.
patent: 5041746 (1991-08-01), Webster
patent: 5162680 (1992-11-01), Norman
patent: 5297093 (1994-03-01), Coffman
patent: 5332929 (1994-07-01), Chiang
patent: 5410268 (1995-04-01), Sharpe-Geisler

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