Semiconductor with increased gate coupling coefficient

Details Semiconductor with increased gate coupling coefficient Semiconductor with increased gate coupling coefficient

2000-02-24

2002-09-10

Eckert, II, George C. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S317000, C257S510000, C257S515000, C438S296000

Reexamination Certificate

active

06448606

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically to high gate constant, shallow trench isolation semiconductor memory devices.
BACKGROUND ART
Flash EEPROMs (electrically erasable programmable read only memories) are a class of nonvolatile semiconductor memory devices that are programmed by hot electron injection and erased by Fowler-Nordheim tunneling. Each memory cell is formed on a semiconductor substrate (i.e., a silicon die or chip) having a heavily doped drain region and a source region embedded therein. The source region further contains a lightly doped, deeply diffused region and a more heavily doped, shallow diffused region embedded into the substrate. A channel region separates the drain region and the source region. The memory cell further includes a multi-layer structure, commonly referred to as a “stacked gate” structure or word line. The stacked gate structure typically includes: a thin gate dielectric or tunnel oxide layer formed on the surface of substrate overlying the channel region; a polysilicon (poly) floating gate overlying the tunnel oxide; an interpoly dielectric overlying the floating gate; and a poly control gate overlying the interpoly dielectric layer. Additional layers, such as a silicide layer (disposed on the control gate), a poly cap layer (disposed on the silicide layer), and a silicon oxynitride layer (disposed on the poly cap layer) may be formed over the control gate. A plurality of Flash EEPROM cells may be formed on a single substrate.
A Flash EEPROM also includes peripheral portions which typically include input/output circuitry for selectively addressing individual memory cells.
The process of forming Flash EEPROM cells is well known and widely practiced throughout the semiconductor industry. After the formation of the memory cells, electrical connections, commonly known as “contacts”, must be made to connect the stacked gate structures, the source region, and the drain regions to other part of the chip.
The contact process starts with the formation of sidewall spacers around the stacked gate structures of each memory cell. An etch stop or liner layer, typically a nitride material such silicon nitride, is then formed over the entire substrate, including the stacked gate structure, using conventional techniques, such as chemical vapor deposition (CVD). A dielectric layer, generally of oxide such as boro-phospho-tetra-ethyl-ortho silicate (BPTEOS) or borophosphosilicate glass (BPSG), is then deposited over the etch stop layer. A layer of photoresist is then placed over the dielectric layer and is photolithographically processed to form a photoresist mask having the pattern of contact openings. An an isotropic etch is then used to etch out portions of the dielectric layer to form source and drain contact openings in the oxide layer. The contact openings stop at the source and drain regions in the substrate. The photoresist mask is then stripped, and a conductive material, such as tungsten, is deposited over the dielectric layer and fills the source and drain contact openings to form so-called “self-aligned contacts” (conductive contacts). The substrate is then subjected to a chemical-mechanical polishing (CMP) process which removes the conductive material above the dielectric layer to form the conductive contacts through a contact CMP process.
For miniaturization, it is desirable to dispose the Flash EEPROM cells as closely together as possible. A commonly used process to achieve bit line isolation between the memory cells is local oxidation of silicon (LOCOS) isolation. A problem associated with LOCOS isolation is that some of the LOCOS isolation gets consumed during processing, which creates a surface area profile resembling a bird's beak. The bird's beak surface area profile adds to the minimum dimension between adjacent Flash EEPROM cells and is becoming more problematic as separation between adjacent memory cells diminishes.
Further simplification to reduce the number of process steps is also desirable. Each additional process step introduces added cost, time, and potential manufacturing defects. Therefore, there is always a need to streamline processing by reducing the number of independent masks needed to produce the Flash EEPROM cells.
Another problem associated with Flash EEPROM cells is maintaining the gate coupling coefficient (C
G
). The C
G
is the ratio of the floating voltage with respect to the control voltage. A larger C
G
corresponds to greater device efficiency.
A solution, which would allow further miniaturization of semiconductor memory devices without adversely affecting device performance has long been sought, but has eluded those skilled in the art. As the demand for higher performance devices and miniaturization at reduced costs continues at a rapid pace in the semiconductor field, it is becoming more pressing that a solution be found.
DISCLOSURE OF THE INVENTION
The present invention provides a method for reducing semiconductor device geometry by using shallow trench isolation for bit line isolation of floating gates.
The present invention further provides a method for reducing semiconductor device geometry by eliminating the bird's beak phenomenon of local oxidation of silicon (LOCOS) isolation to enable semiconductor gate structures to be positioned closer together.
The present invention further provides a method for forming a semiconductor device that provides increased gate coupling coefficient for greater device efficiency.
The present invention further provides a method for forming a semiconductor device that increases the surface area of the insulator disposed between the control gate and the floating gate of an EEPROM device for greater device efficiency.
The present invention further provides a method for reducing the number of process steps to manufacture semiconductor gate structures.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5051795 (1991-09-01), Gill et al.
patent: 5622881 (1997-04-01), Acocella et al.
patent: 5698879 (1997-12-01), Aritome et al.
patent: 5946230 (1999-08-01), Shimizu et al.
patent: 6130129 (2000-10-01), Chen
patent: 6159801 (2000-12-01), Hsieh et al.
patent: 6222225 (2001-04-01), Nakamura et al.
patent: 6281103 (2001-08-01), Doan
patent: 6323516 (2001-11-01), Wang et al.
patent: 4-11-103033 (1999-04-01), None
Aritome et al., A 0.67um Self-Aligned Shallow Trench Isolation Cell (SA-STI Cell) for 3V-only 256 Mbit NAND EEPROMS, 1994, ieee, iedm-94, pp. 61-64.*
Guillaumot et al., Flash EEPROM Cells Using Shallow Trench Isolation, 1996, IEEE Int'l NonVolatile Memory Technology Conference, pp. 74-75.

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