Semiconductor with a nitrided silicon gate oxide and method

Details Semiconductor with a nitrided silicon gate oxide and method Semiconductor with a nitrided silicon gate oxide and method

2002-12-20

2004-04-06

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S591000, C438S585000, C438S770000, C438S775000

Reexamination Certificate

active

06716695

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of integrated circuit fabrication, and more particularly to a semiconductor with a nitrided silicon gate oxide and a method for forming same.
BACKGROUND OF THE INVENTION
Presently, there is a great demand for shrinking semiconductor devices to provide an increased density of devices on the semiconductor chip that are faster and consume less power. The scaling of devices in the lateral dimension requires vertical scaling as well so as to achieve adequate device performance.
Gate stacks may comprise a gate oxide overlying a gate dielectric. The gate oxide may comprise silicon dioxide or, more recently, a nitrided gate oxide. Traditionally, plasma-assisted nitridation of silicon oxide to form nitrided gate oxide structures is achieved by creating a silicon dioxide layer on the surface of a substrate and reacting the silicon dioxide layer with ionized nitrogen generated by a plasma source.
SUMMARY OF THE INVENTION
A method of fabricating a transistor includes providing a semiconductor substrate having a surface and forming a nitride layer outwardly of the surface of the substrate. The nitride layer is oxidized to form a nitrided silicon oxide layer comprising an oxide layer beneath the nitride layer. A high-K layer is deposited outwardly of the nitride layer, and a conductive layer is formed outwardly of the high-K layer. The conductive layer, the high-K layer, and the nitrided silicon oxide layer are etched and patterned to form a gate stack. Sidewall spacers are formed outwardly of the semiconductor substrate adjacent to the gate stack, and source/drain regions are formed in the semiconductor substrate adjacent to the sidewall spacers.
Technical advantages of the present invention include an improved gate dielectric with low nitrogen incorporation in the substrate. The low nitrogen incorporation increases electron mobility and limits voltage shift. In addition, low nitrogen incorporation limits migration of oxygen atoms into the substrate and thus increases the efficiency of transistor components.
Certain embodiments may possess none, one, some, or all of these technical features and advantages and/or additional technical features and advantages. Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.


REFERENCES:
patent: 6511876 (2003-01-01), Buchanan et al.
patent: 2001/0002709 (2001-06-01), Wallace et al.
patent: 2002/0197789 (2002-12-01), Buchanan et al.
patent: 2003/0116804 (2003-06-01), Visokay et al.

Affiliated with

Also associated with

Rating

Semiconductor with a nitrided silicon gate oxide and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor with a nitrided silicon gate oxide and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor with a nitrided silicon gate oxide and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3221874