Semiconductor wiring structures including dielectric cap...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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Details

C257S758000, C257S774000, C257SE23141, C438S648000

Reexamination Certificate

active

07732924

ABSTRACT:
Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring line, and a local dielectric cap positioned within a portion of the metal cap layer and in contact with the metal wiring line and a related method are disclosed. The local dielectric cap represents an intentionally created weak point in the metal wiring line of a dual-damascene interconnect, which induces electromigration (EM) voiding in the line, rather than at the bottom of a via extending downwardly from the metal wiring line. Since the critical void size in line fails, especially with metal cap layer (liner) redundancy, is much larger than that in via fails, the EM lifetime can be significantly increased.

REFERENCES:
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patent: 5695810 (1997-12-01), Dubin et al.
patent: 6323554 (2001-11-01), Joshi et al.
patent: 6342733 (2002-01-01), Hu et al.
patent: 6383920 (2002-05-01), Wang et al.
patent: 6635496 (2003-10-01), Ning
patent: 2004/0113279 (2004-06-01), Chen et al.
Hu et al., “Effect of metal liner on electromigration in Cu Damascene lines,” Journal of Applied Physics 98, 124501, 2005, pp. 124501-1-124501-8.
Hu et al., “Comparison of Cu electromigration lifetime in Cu Interconnects coated with various caps,” Applied Physics Letters, vol. 83, No. 5, Aug. 4, 2003, pp. 869-871.

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