Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-08-13
2003-06-24
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S631000, C438S645000
Reexamination Certificate
active
06583050
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor wafer with improved flatness in the peripheral area and to a process for producing a semiconductor wafer of this nature. Semiconductor wafers with a high degree of flatness are suitable for use in the semiconductor industry, in particular for the manufacture of electronic components with line widths of less than or equal to 0.13 &mgr;m.
2. The Prior Art
A semiconductor wafer which is intended to be suitable in particular for the manufacture of electronic components with line widths of less than or equal to 0.13 &mgr;m must have a large number of special properties. A particularly important property is the local flatness of the semiconductor wafer. The modern stepper technology requires optimum local flatness in all partial areas of a side of the semiconductor wafer. The back-surface-referenced global (GBIR; previously also known as TTV) and local (SBIR; previously also known as LTV) flatness measurements which were in widespread use in the past are being replaced by flatness measurements which take into account the focusing ability of a stepper in all partial areas of the wafer surface. Such a flatness measurement is the SFQR (site front-surface referenced least squares/range=range of the positive and negative deviation from a front surface defined by minimizing the mean square error for a component area of defined size). The value SFQR
max
indicates the maximum SFQR value for all the component areas on a semiconductor wafer. A generally accepted rule of thumb states that the SFQR
max
value of a semiconductor wafer must be less than or equal to the possible line width on this wafer for semiconductor components which can be produced on it. If this value is exceeded, the stepper experiences focusing problems and the component in question will be lost.
The final flatness of a semiconductor wafer is generally produced by a polishing process. Equipment and processes for the simultaneous polishing of front and back surfaces of a semiconductor wafer, in order to improve the flatness values of the semiconductor wafer, have been put in place and refined. This so-called double-side polishing is described, for example, in U.S. Pat. No. 3,691,694.
Double-side polishing is also described in EP 208 315 B1. Semiconductor wafers are in carriers which are made from metal or a plastics material and have suitably dimensioned cutouts. The wafers and carriers are moved along a path which is predetermined by the machine and process parameters between two rotating polishing plates. These plates are covered with a polishing cloth, and are in the presence of a polishing fluid; and the wafers are thusly polished (in the specialist literature, carriers are also referred to as templates). The pressure forces which are employed during double-side polishing act preferentially on the semiconductor wafer which is to be polished and not on the carrier. To achieve this result, the end thickness of semiconductor wafers which have undergone double-side polishing according to the prior art is considerably thicker than that of the carriers used. For example, E. Mendel and J. R. Hause, in
IBM Technical Report
TR22.2342, presented at the
Spring Meeting of the Electrochemical Society in Boston
, Mass. on May 10, 1979, recommend that the wafers project by 2 to 3 mil (corresponds to 51 to 76 &mgr;m). This degree of projection can be ensured either by establishing the polishing time required on the basis of the material-abrasion rates determined in preliminary tests for a specific test procedure or by means of spacers arranged on the carrier. This is described in U.S. Pat. No. 5,422,316.
It is known to integrate double-side polishing into process sequences for producing semiconductor wafers. EP 754 785 A1 describes the sequence of sawing a semiconductor crystal, followed by edge rounding, double-side polishing and final polishing of the semiconductor wafers obtained. In EP 755 751 A1, it is proposed to employ a double-side grinding process between the edge rounding and the double-side polishing. The preferred embodiments described in U.S. Pat. No. 5,756,399 include the process sequence of sawing-edge rounding-grinding-alkaline etching-double-side polishing.
DE153 33 257 C1 describes the process sequence of sawing-edge rounding-grinding-etching-double-side polishing-final polishing. The etching in this case is carried out using an improved acid etching process. A common feature of these process sequences is that after the double-side polishing they lead to a semiconductor wafer which has higher local geometry values, expressed as SFQR, in the peripheral area than in the central area of the semiconductor wafer. Under certain conditions procedures such as that described in EP 187 307 A1, are aimed at compensating for the thinner edges by providing an initial dish-like geometry. This may lead to an improvement in the rear-surface-referenced geometry values GBIR and SBIR. However, such procedures represent a disadvantage with regard to the SFQR values which are relevant for the production of components.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor wafer which is suitable in particular for the manufacture of electronic components with line widths of less than or equal to 0.13 &mgr;m and which does not have the abovementioned drawbacks with regard to the local geometry in the peripheral area, expressed as SFQR. Furthermore, the further properties of the semiconductor wafer should be at least equal to those of semiconductor wafers produced according to the prior art, and there should be advantages in terms of production costs.
The present invention is directed to a semiconductor wafer with a front surface and a back surface and flatness values based on partial areas of a surface grid on the front surface of the semiconductor wafer, which has a maximum local flatness value SFQR
max
of less than or equal to 0.13 &mgr;m and individual SFQR values which in a peripheral area of the semiconductor wafer do not differ significantly from those in a central area of the semiconductor wafer.
Preferably, in this context, there is considered to be no significant difference between individual SFQR values in the peripheral area and the central area if the arithmetic mean of the SFQR values for the peripheral area differs by at most 0.03 &mgr;m from the arithmetic mean of the SFQR values for the central area.
The present invention is also directed a process for producing a semiconductor wafer by simultaneously polishing of a front surface and a back surface of the semiconductor wafer between rotating polishing plates while a polishing fluid is being supplied, the semiconductor wafer lying in a cutout in a carrier and being held on a specific geometric path, and the carrier being of defined thickness, and the semiconductor wafer having a starting thickness prior to polishing and an end thickness after polishing, wherein the starting thickness of the semiconductor wafer is 20 to 200 &mgr;m greater than the thickness of the carrier and the semiconductor wafer is polished until the end thickness of the semiconductor wafer is 2 to 20 &mgr;m greater than the thickness of the carrier.
The essential feature of the invention is that the semiconductor wafer must be subjected to double-side polishing until the thickness of the final polished semiconductor wafer is only slightly greater than the thickness of the carrier used. The thickness difference must lie within a narrow window of from 2 to 20 &mgr;m. As the examples given below will illustrate, the discovery of this window was surprising and impossible to foresee.
The starting material used for the process is a semiconductor wafer which has been separated in a known way from a crystal. For example it may be separated from a silicon single crystal which has been cut to length and undergone circular grinding and the front and/or back surfaces of which have undergone a surface-grinding step. If desired, the crystal may be provided with one or
Altmann Thomas
Bernwinkler Willibald
Feuchtinger Ernst
Heier Gerhard
Wenski Guido
Collard & Roe P.C.
Dang Phuc T.
Nelms David
Wacker Siltronic Gesellschaft F{dot over (u)}r Halbleitermateria
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