Electricity: electrical systems and devices – Electric charge generating or conducting means – Use of forces of electric charge or field
Reexamination Certificate
2001-03-30
2003-11-11
Jackson, Stephen W. (Department: 2836)
Electricity: electrical systems and devices
Electric charge generating or conducting means
Use of forces of electric charge or field
C361S233000, C361S160000
Reexamination Certificate
active
06646857
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor fabrication equipment, and more particularly, the present invention relates to an improved mechanism for de-chucking and lifting a semiconductor wafer from a chuck that resides inside a semiconductor processing chamber.
2. Description of the Related Art
In semiconductor fabrication, integrated circuit devices are fabricated from semiconductor wafers that are placed through numerous processing operations. Many of the numerous processing operations are commonly carried out in processing chambers in which layers, such as, dielectric and metallization materials are successively applied and patterned to form multi-layered structures. For example, some of these layers (e.g., SiO
2
) are commonly deposited in chemical vapor deposition (CVD) chambers, and then photoresist materials are spin-coated and placed through photolithography patterning. When a photoresist mask is defined over a particular surface, the semiconductor wafer is placed into a plasma etching chamber in order to remove (i.e., etch) portions of the underlying materials that are not covered by the photoresist mask.
FIG. 1A
shows a semiconductor processing system
100
including a chamber
102
that is used for processing semiconductor wafers through etching operations. In this example, the chamber
102
includes a chuck
104
which is configured to support a semiconductor wafer
106
. The chamber
102
is also configured to have a top electrode
114
. The top electrode
114
is configured to receive processing gases which are distributed into the plasma region
112
during processing. The plasma region
112
is defined between the surface of the top electrode
114
and the surface of the wafer
106
.
The top electrode
114
is also shown coupled to a match box
116
a
and an RF power source
118
a.
The chuck
104
is also coupled to a match box
116
b
and an RF power source
118
b.
The chamber
102
is provided with outlets
120
which are configured to pump out excess gases from within the chamber
102
during processing. In operation, the RF power supply
118
a
is configured to bias the top electrode
114
and operate at frequencies of about 27 MHz. The RF power source
118
a
is primarily responsible for generating most of the plasma density within the plasma region
112
, while the RF power source
118
b
is primarily responsible for generating a bias voltage within the plasma region
112
. The RF power source
118
b
generally operates at lower frequencies in the range of about 2 MHz.
FIGS. 1B and 1C
provide a more detailed view of the chuck
104
of the semiconductor processing system
100
. The chuck
104
shown in
FIG. 1B
is of the monopolar type in which only one positive electrode
122
is formed in dielectric material
124
and the plasma
112
potential has a negative polarity. The chuck
104
shown in
FIG. 1C
is of the bipolar type in which two electrodes, namely, positive electrode
130
and negative electrode
132
, are formed in dielectric material
124
.
As shown in
FIGS. 1B and 1C
, the chuck
104
contains a number of penetrations
126
through which lifting pins
128
are pneumatically actuated to lift the semiconductor wafer
106
from the chuck
104
upon completion of the processing operation. The process of removing the wafer
106
from the chuck
104
at the completion of processing is commonly referred to as a “de-chucking” process. Under optimal de-chucking processes, the wafer is simply lifted off of the chuck
104
using the pneumatic controls, and can then be removed from the processing chamber
100
.
FIG. 1D
presents a flowchart diagram describing a conventional de-chucking operation.
FIG. 1D
beings at the completion of semiconductor wafer processing
140
. The wafer
106
must then be allowed to fully discharge
142
before attempting to lift it from the chuck
104
. For monopolar chucks as shown in
FIG. 1B
, wafer discharge occurs through the plasma region, and in most systems requires approximately 120 seconds to complete with minimal residual charge on the wafer
106
. For bipolar chucks
104
as shown in
FIG. 1C
, normal wafer discharge through the plasma
112
is supplemented by discharge through the chuck
104
which is facilitated with the bipolar electrodes. Wafer
106
discharge through the bipolar chuck typically requires approximately 10 to 180 seconds. The bipolar chuck assembly is advantageous as it minimizes the time required for wafer discharge and directly improves processing cycles and throughput. However, the discharge process commonly results in residual charges that are non-uniformly distributed throughout the wafer. As will be discussed below, the presence of residual charge whether uniform or un-uniform can lead to wafer damaging repercussions.
Upon completion of wafer discharge,
FIG. 1D
continues with actuation
144
of the lifting pins
128
to clear the wafer
106
from the chuck
104
and allow removal of the wafer
106
from the system. Actuation of the lifting pins (typically 3 or 4) is usually achieved through use of pneumatic force. The lifting pins
128
travel upward to contact the bottom wafer surface and lift the wafer
106
to a preset transfer height. Once at transfer height, the wafer
106
is removed
146
from the system. If another wafer
106
is to be processed, the next wafer
106
is placed
148
on the lifting pins
128
, lowered
150
to the chuck
104
, and the process in
FIG. 1D
is repeated.
Lifting of the wafer
106
from the chuck
104
occasionally results in irreparable damage to the wafer
106
. This damage is usually caused through contact between the lifting pins
128
and the wafer
106
. If the wafer
106
contains sufficient residual charge, which is commonly non-uniform, the wafer
106
will remain electrostatically attached to the chuck
104
when the lifting pins
128
are actuated. For pneumatically actuated lifting pins
128
, the lifting pins
128
are moved with a constant non-adjustable force and velocity. Thus, when impacting an immovable wafer (e.g., attached), the lifting pins will do damage to the wafer
106
. If the wafer
106
is lifted only on one side (as is know to occur), the wafer
106
will slide off of the chuck
104
and become damaged. In some cases, the wafer will actually break or will cause irreversible damage to fabricated circuitry. Also, if the pin lifting force is initially resisted by the wafer
106
through residual electrostatic attraction with the chuck
104
, the wafer
106
may suddenly be released from the chuck
104
as the wafer discharge process continues while the pin lifting force is applied. This sudden release from the chuck
104
may result in projectile motion of the wafer
106
and associated damage. In other cases, if the wafer
106
contains sufficient residual charge and the lifting pins
128
are applied with sufficient force, the lifting pins may actually break through the wafer.
In view of the foregoing, what is needed is a pin lifting apparatus, and method for making and implementing the apparatus which will assist in efficiently lifting the semiconductor wafer from the chuck through the application of monitored and controlled lifting force to the backside of a wafer and provide techniques for rapid removal of resistant residual charges between the wafer and chuck.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing an apparatus and method for controllably lifting a wafer off of an electrostatic chuck after a processing operation. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, in a wafer processing chamber, a wafer lifting mechanism for controlling the lifting of the wafer off of an electrostatic chuck at a completion of processing is disclosed. The wafer lifting mechanism includes a pin lifter yoke that is orien
Anderson Thomas W.
Sexton Greg S.
Jackson Stephen W.
Lam Research Corporation
Martine & Penilla LLP
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