Semiconductor wafer level interconnect package utilizing...

Details Semiconductor wafer level interconnect package utilizing... Semiconductor wafer level interconnect package utilizing...

2007-12-06

2010-11-23

Cao, Phat X (Department: 2814)

Semiconductor device manufacturing: process

Semiconductor substrate dicing

Having specified scribe region structure

C438S460000, C438S464000, C257SE23014, C257SE23012, C257SE23011, C257SE23168, C257SE23141, C257S730000, C257S698000, C257S690000, C257S691000, C257S692000, C257S693000, C257S694000

Reexamination Certificate

active

07838395

ABSTRACT:
A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Through hole vias (THV) are formed in the die extension region. A conductive plane or ring is formed in a center area on the active surface of the semiconductor die. The conductive plane or ring is coupled to a first contact pad for providing a first power supply potential to the active circuits. The conductive plane or ring is electrically connected to a first THV. A conductive ring is formed partially around a perimeter of the conduction plane or ring. The conductive ring is coupled to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.

REFERENCES:
patent: 6181569 (2001-01-01), Chakravorty
patent: 6368896 (2002-04-01), Farnworth et al.
patent: 6492719 (2002-12-01), Miyamoto et al.
patent: 6608377 (2003-08-01), Chang et al.
patent: 2006/0197234 (2006-09-01), Pape
patent: 2009/0008793 (2009-01-01), Pohl et al.
patent: 2004214501 (2004-07-01), None

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