Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Outside periphery of package having specified shape or...
Reexamination Certificate
2003-10-10
2008-05-13
Pham, Hoai v (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Outside periphery of package having specified shape or...
C257S618000, C257SE23179
Reexamination Certificate
active
07372150
ABSTRACT:
A semiconductor wafer including an identification indication is provided. The wafer includes a convex edge with an upper surface area and a lower surface area. The identification indication is in a marking region which is disposed on a lower side surface of the convex edge. The lower side surface has a wide region where the marking region is located. This wide region has a width that is wider than an upper side surface of the wafer and thus makes a cross-section of a side of the wafer asymmetrical. With the present invention, the entire top surface of the semiconductor wafer can be utilized for a semiconductor chip region and prevents manufacturing problems associated with the uneven nature of the identification indication when the identification is located on the top surface of the wafer.
REFERENCES:
patent: 101 31 246 (2005-02-01), None
patent: 59023512 (1984-02-01), None
patent: 10-256105 (1998-09-01), None
patent: 000057827 (2000-09-01), None
English Language Abstract of Japan Publication No: 10-256105.
English Language Abstract of Korean Publication No: 000057827 A.
Cho Kyoo-Chul
Choi Sam-Jong
Chung Hoe-Sik
Han Shin-Hyeok
Kim Gi-Jung
Marger & Johnson & McCollom, P.C.
Nguyen Dilinh
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