Semiconductor wafer and testing method therefor

Details Semiconductor wafer and testing method therefor Semiconductor wafer and testing method therefor

2007-01-30

2007-01-30

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C257S048000, C257SE23179, C257SE21584, C257SE21524, C324S765010

Reexamination Certificate

active

11245091

ABSTRACT:
Circuits under electrode terminals and a nonconductor layer of the electrode terminals in semiconductor devices are prevented from being damaged during a test, such as a burn-in test, on the semiconductor devices formed on a wafer. Alignment patterns provided on the semiconductor wafer have detector electrode terminals and conductor electrode terminals. A detector electrode terminal surrounds a conductor electrode terminal separated by a gap from the detector electrode terminals and a portion of the surrounding detector electrode terminal is open.

REFERENCES:
patent: 5321277 (1994-06-01), Sparks et al.
patent: 6087719 (2000-07-01), Tsunashima
patent: 6133054 (2000-10-01), Henson
patent: 6133582 (2000-10-01), Osann et al.
patent: 6380555 (2002-04-01), Hembree et al.
patent: 6781150 (2004-08-01), Low et al.
patent: 6781365 (2004-08-01), Hu
patent: 6881597 (2005-04-01), Asayama et al.
patent: 2002/0164840 (2002-11-01), Lu et al.
patent: 2003/0122246 (2003-07-01), Lin et al.
patent: 5-343487 (1993-12-01), None
patent: 6-45419 (1994-02-01), None

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