Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate
Reexamination Certificate
2001-08-13
2004-08-10
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having junction gate
C438S202000, C438S313000, C438S322000, C257S197000, C257S273000
Reexamination Certificate
active
06773973
ABSTRACT:
TECHNICAL FIELD
This invention relates to a semiconductor transistor having a polysilicon emitter and methods of making the same.
BACKGROUND
Transistors with polysilicon emitters generally have high current gains compared to transistors with metal emitters.
FIG. 1
shows a conventional polysilicon emitter transistor
50
. The polysilicon emitter
50
includes a collector region
52
, a single crystal silicon base region
54
, and an oxide layer
56
. An emitter window
60
is created through the oxide layer
56
and is filled with an undoped polysilicon layer
58
. Subsequently, the undoped polysilicon layer
58
is doped using ion implantation and annealed at a high temperature to diffuse the dopants onto the underlying single crystal silicon base region
54
. Polysilicon emitter transistors may also be formed using an in-situ doped polysilicon layer.
However, as a result of the deposition of the polysilicon layer
58
, the grain size of the polysilicon layer
58
may increase to the extent of forming a single crystal epitaxy. The grain size is illustrated in
FIG. 1
where reference number
62
indicates a boundary between grains. Often, the grain size of the polysilicon layer
58
is comparable to the size of the emitter window
60
. The grain size may limit the size of the emitter window
60
and thus may limit the size of the transistor device
50
. In addition, the resulting grain size may have the undesirable effect of preventing uniform diffusion of dopants from the polysilicon layer
58
to the base region
54
. The non-uniform diffusion of dopants may have a negative impact on the current gain of the polysilicon emitter transistor
50
. Moreover, the use of in-situ doped polysilicon may have an even greater negative effect on the current gain of the transistor
50
than the use of undoped polysilicon that is subsequently doped.
SUMMARY
The invention provides polysilicon-emitter transistor devices that overcome limitations of prior art devices. According to one aspect of the invention, a polysilicon emitter transistor includes a transistor having an emitter window exposing a base region of the transistor. A first polysilicon layer is deposited within the emitter window at least on the base region. An interfacial oxide layer is then formed, for example, by annealing the first polysilicon layer. Then, a second polysilicon layer is formed on the interfacial oxide layer.
In different embodiments, the emitter window may be approximately 0.1 to 0.2 &mgr;m wide, and the first polysilicon layer may be approximately 30 to 100 Angstroms (Å) thick prior to formation of the interfacial oxide. The interfacial oxide may be approximately 5 to 50 Å thick and can be thermally grown. The second polysilicon layer may be approximately 500 to 5000 Å thick and dopants can be ion-implanted in the second polysilicon layer. An annealing process may also be applied after deposition of the second polysilicon layer.
Advantages of the invention include one or more of the following. The polysilicon grain size in the region of the emitter adjacent to the base region is smaller, and because of this, smaller polysilicon-emiter transistors may be realized and the diffusion of dopants from the emitter to base is more uniform. The uniform diffusion of dopants also can increase the current gain and the speed of the transistor. The interfacial oxide layer may also improve the flow of majority carriers through the emitter diffusion region and into the intrinsic base sub-region without having to heavily dope the intrinsic base sub-region. Also, transistors may be made with a thinner emitter diffusion region and a narrower intrinsic base sub-region. As a result, the current gain and speed performance of the transistor may be improved without negatively impacting the resistance of the intrinsic base sub-region or the resistance of the emitter diffusion region.
The techniques disclosed are applicable to any polysilicon-emitter transistor device regardless of the type of dielectric or oxide layer deposited on the base region. The invention also applies to bipolar transistors used in bipolar-complementary metallic oxide semiconductors (Bi-CMOS) semiconductor devices.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
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Ashburn, “Polysilicon Emitter Technology,”Proceedings of the 1989 Bipolar Circuits and Technology Meeting, Minneapolis Marriott City Center Hotel, Sep. 18-19, 1989, Sponsored by IEEE Electron Devices Society, pp. 90-97.
Burghartz et al., “Perimeter and Plug Effects in Deep Sub-Micron Polysilicon Emitter Bipolar Transistors,”1990 Symposium on VLSI Technology—Digest of Technical Papers, 1990, pp. 55-56.
Decoutere et al., “A Unified Approach for Hot-Carrier Degradation of Current Gain and 1/f Noise of Polysilicon Emitter Bipolar Transistors,”Proceedings of the 1997 Bipolar/BiCMOS Circuits and Technology Meeting, Sep. 28-30, 1997, Sponsored by IEEE Electron Devices Society, pp. 104-107.
Reuss et al., “Effects of Interfacial Oxide on Hot Carrier Reliability of Polysilicon Emitter npn Transistors,”Proceedings of the 1993 Bipolar/BiCMOS Circuits and Technology Meeting, 1993, Sponsored by IEEE Electron Devices Society, pp. 219-222.
Kalnitsky Alexander
Park Sang
Uppili Sudarsan
Blakely , Sokoloff, Taylor & Zafman LLP
Fourson George
Maxim Integrated Products Inc.
Toledo Fernando L.
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