Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-11-20
2001-10-30
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000
Reexamination Certificate
active
06311300
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor testing apparatus, and more particularly, for a semiconductor testing apparatus for testing a semiconductor device including a built in self test circuit.
2. Description of the Background Art
In a conventional IC test, a number of test channels are provided and each channel, test signals each having a prescribed test waveform in accordance with the condition of testing, that is, a test signal having a prescribed voltage level and a prescribed timing of waveform change is formed, and the test signals are applied to respective corresponding pins of an IC to be tested, whereby electrical characteristic of the IC has been tested.
FIG. 8
is a block diagram showing the structure of a conventional IC tester
50
. Referring to
FIG. 8
, a test flow or a test condition is programmed in accordance with test specification, in an IC tester control CPU
51
of IC tester
50
. IC tester control CPU
51
applies a control signal to various circuits of IC tester
50
and sets data of various circuits, through control signal transfer bus
52
as needed. A reference signal generating circuit
53
generates an operational reference signal of IC tester
50
. The reference signal serves as a reference of the period of changing condition of the test waveform (hereinafter referred to as test period). The reference signal is applied to a timing generator
55
and a program power supply
60
.
Timing generator
55
controls timing of change of the test waveform and so on. More specifically, before each test, IC tester control CPU
51
sets data of test condition, and applies necessary data for every test period to timing generator
55
through an internal address bus
54
. Timing generator
55
programmably generates the test period set by IC tester control CPU
51
.
A test pattern storing circuit
56
determines a pattern of test waveform for each test period. More specifically, IC tester control CPU
51
stores a test pattern at a prescribed address of test pattern storing circuit
56
before test, and during testing, applies an address signal to test pattern storing circuit
56
. In response to the applied address signal, test pattern storing circuit
56
outputs the test pattern.
Test pattern generator
57
for function test is formed of a high speed microcomputer, and generates address and data and controls clocks, in accordance with a microprogram. A format circuit
58
synthesizes a timing signal applied from timing generator
55
, a test pattern applied from test pattern storing circuit
56
and logic data applied from test pattern generator
57
for function test, for each test period, and generates a test waveform. Timing generator
55
, test pattern storing circuit
56
and format circuit
58
constitute a waveform generating circuit
59
.
Program power supply
60
includes a bias power supply for supplying a power supply voltage to IC
70
to be tested, and a data level power supply for determining levels of a driver and a comparator of pin electronics
61
. Pin electronics
61
includes a driver, a comparator and a group of relays connecting these to IC
70
to be tested, and is coupled to IC
70
to be tested through a contact terminal
71
. The driver generates a test signal to be applied to IC
70
to be tested based on the test waveform applied from waveform forming circuit
59
and a voltage value applied from program power supply
60
. The comparator determines whether an output waveform of IC
70
under test is normal or not, based on the timing signal applied from timing generator
55
and the voltage value applied from program power supply
60
. The result of determination is applied to a defective address storing circuit
62
through test pattern generator
57
for function test.
Defective address storing circuit
62
stores information of defective address of tested IC
70
applied from test pattern generator
57
for function test. A defect analyzing circuit
63
performs redundancy analysis of tested IC
70
, for example, based on the information of defective address applied from defective address storing circuit
62
.
In this manner, conventional IC tester
50
directly tested electrical characteristics of IC
70
through various pins of IC
70
to be tested. IC tester
50
must have channels, that is, waveform forming circuits
59
, pin electronics drivers and so on, the number of which corresponds to the number of pins of IC
70
to be tested, and therefore, as an IC comes to have larger number of pins, the number of test channels is also increased, resulting in high cost of the tester. Further, the number of ICs which can be tested at one time by one tester is reduced, lowering efficiency of testing.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a semiconductor testing apparatus which attains improved test efficiency and lowers cost of testing.
Briefly stated, according to the present invention, a built in self test circuit is provided in a semiconductor device having a memory circuit, and in the semiconductor test apparatus, a power supply for applying a power supply voltage to the semiconductor device, an instructing circuit for instructing execution of a test and output of data indicative of the test result to the self test circuit, and a receiving circuit for receiving data output from the self test circuit are provided. Therefore, as compared with the prior art in which an address signal and a control signal are applied to the semiconductor device, the number of terminals for signal output and the number of pattern generators can be reduced, the number of semiconductor devices which can be tested at one time per one semiconductor testing apparatus is increased, and therefore the cost of testing is reduced and efficiency of testing is improved.
Preferably, the semiconductor device further includes a logic circuit, and the built in self test circuit tests at least a part of the logic circuit. Here, the cost of testing a semiconductor device including a memory circuit and a logic circuit can be reduced and test efficiency can be improved.
More preferably, a test circuit for testing that portion of the logic circuit which is not tested by the built in self test circuit is further provided. Here, burden on the built in self test circuit can be reduced, and the structure of the built in self test circuit is simplified.
Preferably, a clock generating circuit for applying a clock signal for synchronization between the semiconductor test apparatus and the built in self test circuit is further provided. Accordingly, synchronization between the semiconductor device and the semiconductor testing apparatus can readily and surely be attained.
Preferably, the built in self test circuit outputs data n bits by n bits, and the receiving circuit includes a serial/parallel converting circuit for generating, from the data output n bits by n bits from the built in self test circuit, parallel data of predetermined n×m bits, and storing apparatus for storing the parallel data generated by the serial/parallel converting circuit. When the value n is small, only a small number of data output pins is necessary, and if the value n is large, the time for data output is reduced.
Preferably, the semiconductor testing apparatus tests a plurality of semiconductor devices at one time, the serial/parallel converting circuit of the receiving circuit is provided corresponding to each of the semiconductor devices, and the receiving circuit further includes a buffer circuit for temporarily storing the plurality of parallel data generated by the plurality of serial/parallel converting circuits and successively applying each of the plurality of parallel data to the storing apparatus. Accordingly, while the buffer circuit is outputting data, the next data can be applied to the serial/parallel converting circuit, and therefore the time for testing can be reduced.
Preferably, the semiconductor testing apparatus tests a plurality of semiconductor devices simultaneou
Omura Ryuji
Shibayama Mari
Sugiura Kazushi
Chung Phung M.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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