Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-08-14
2007-08-14
Kerveros, James C (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
10495717
ABSTRACT:
A semiconductor testing apparatus capable of reducing time required for testing or repairing a plurality of semiconductor devices. The semiconductor testing apparatus performs test for a plurality of DUT in parallel and performs repair for the plurality of DUT in parallel. For this, the apparatus includes an ALPG, a PDS, an AFM, a driver pin processor, an IO pin processor, a driver channel, and an IO channel. The IO pin processor has a plurality of sub-FC units. When test is performed simultaneously for a plurality of DUT, an individual pattern waveform is generated corresponding to individual information.
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Advantest Corporation
Kerveros James C
Patenttm.us
Walters James H.
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