Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2003-05-06
2008-12-30
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S728000
Reexamination Certificate
active
07472326
ABSTRACT:
A tester and method are provided for testing semiconductor devices. Generally, the tester includes a multitasking Algorithmic Pattern Generator (APG) to concurrently execute multiple programs on multiple test sites using a single pattern generator. In one embodiment, up to eight test programs are run independently and concurrently on eight independent sixteen-pin devices on a 128 pin test site. When the multitasking APG is ready to broadcast to a device, timing system associated with that device only (and not the other devices) are loaded. While the timing system is executing the cycle of the test programs for the device just loaded, the APG continues on to load the other devices. Because of the slow cycle rates required for programming versus reading, the tester is particularly advantageous for testing flash memory. Optionally, for higher throughput, the APG can be run in lock step at up to a maximum operating frequency of the APG during read cycle of flash.
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Britt Cynthia
Dorsey & Whitney LLP
Nextest Systems Corporation
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