Semiconductor test system

Details Semiconductor test system Semiconductor test system

1999-03-09

2002-04-23

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S741000

Reexamination Certificate

active

06378098

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor test system for testing semiconductor integrated circuits such as ICs and LSIs, and more particularly to a semiconductor test system which can efficiently test semiconductor integrated circuits having PLL (phase lock loop) circuits.
BACKGROUND OF THE INVENTION
In testing semiconductor devices such as ICs and LSIs by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test pattern data produced by an IC tester at its appropriate pins at predetermined test timings. The IC tester receives output signals from the IC device under test generated in response to the test pattern data. The output signals are sampled by strobe signals with predetermined timings to be compared with expected data to determine whether the IC device functions correctly.
Some IC devices include therein phase lock loop (PLL) circuits for generating internal clock signals. A phase lock loop (PLL) circuit locks the phase of internal clock signal generated by an internal clock oscillator to the phase of a reference clock signal given from an outside source. Examples of IC devices having PLL circuits include microcomputers and RISC processors. One of the advantages of a PLL circuit is that it can produce a clock signal of reduced jitters or phase fluctuations.
FIG. 3
is a schematic diagram showing a structure for testing an IC device having a phase lock loop circuit by a semiconductor test system. In this example, an IC device under test (DUT)
40
includes a phase lock loop (PLL) circuit
45
to produce an internal clock (PLL clock) signal based on a clock signal received at a clock pin
41
.
Before going into the relationship between the semiconductor test system and the PLL circuit
45
in the DUT
40
, a brief description is made regarding the structure and operation of a PLL circuit. An example of a PLL circuit is shown in
FIG. 5
which is comprised of a phase detector (phase comparator)
46
, a loop filter
47
and a voltage controlled oscillator (VCO)
48
.
The phase detector
46
compares the phase of an input clock signal (CLK) and an oscillation signal (PLL CLK) of the VCO
48
and produces an phase error signal which represents a phase difference between the two signals. Upon receiving the phase error signal from the phase detector
46
, the loop filter
47
converts the phase error signal to an averaged DC voltage. Typically, the loop filter
47
is a low pass filter formed by analog or digital components.
The VCO
48
is an oscillator wherein the oscillation frequency is controlled by the averaged DC voltage of the loop filter
47
. Because of the negative feedback loop, the PLL circuit controls oscillation frequency of the VCO
48
such that the oscillation frequency of the VCO
48
matches with the input clock signal.
The PLL circuit basically performs a two step operation in which the phase synchronization is reached (lock end) after a pull-in step in which the frequency of the VCO
48
approaches close proximity with the reference clock frequency and a lock-in step in which the phase of the two signals are synchronized with one another. By being applied to an inner clock signal (PLL clock), the PLL circuit can reduce the jitters of the clock signal from external sources, or acts as a clock buffer of zero phase delay.
The configuration and function of the semiconductor test system that tests the DUT
40
having the PLL circuit is explained in the following with reference to
FIGS. 3 and 4
. The configuration of
FIG. 3
shows only functional blocks for generating test pattern data and clock signals to be applied to the DUT
40
. The main functional blocks in the semiconductor test system for generating the test pattern data and the clock signal include a timing generator
10
, a pattern generator
20
, and clock and waveform generators
30
0
and
30
1
.
The clock and waveform generators
30
0
and
30
1
commonly receive various signals from the timing generator
10
and the pattern generator
20
. The clock and waveform generator
30
0
provides a clock signal to the clock pin
41
of the DUT
40
and the clock and waveform generator
30
1
provides the test data to the data pin
42
of the DUT. Although only one data pin is shown in
FIG. 3
for the simplicity of explanation, the DUT
40
usually has many data pins such as several tens to several hundreds pins. Accordingly, in an actual semiconductor test system, a large number of clock and waveform generators
30
1
-
30
n
for data pins are prepared, although not shown here.
The timing generator
10
generates a reference clock RCLK
100
, a tester rate signal
200
, and a clear signal
300
. The reference clock RCLK
100
is a reference clock signal of the semiconductor test system produced by a high stable oscillator such as a crystal oscillator. The reference clock RCLK is used to generate clock edges for producing the tester rate signal
200
and the test pattern data
620
. The reference clock RCLK has a frequency of, for example, 100 MHz.
The tester rate signal
200
is also called a test cycle signal and is generated based on desired number of periods of the reference clock RCLK. Generally, timings of test pattern data and strobe signals (not shown) in each test cycle (tester rate) are defined based on a starting edge of the tester rate signal. In a modern semiconductor test system, the time interval of the tester rate signal is dynamically changed under the control of a test program.
The clear signal
300
is to clear (reset) the previous data setting before starting the next set (block) of test patterns. The pattern generator
20
generates the pattern data
600
which includes test data
620
to be applied to the data pin
42
of the DUT
40
and the expected data (not shown) to compare the resultant output of the DUT
40
.
The clock and waveform generator
30
0
generates a clock signal
120
which is applied to the clock pin
41
of the DUT
40
. The clock and waveform generator
30
1
generates the test pattern data
620
which is applied to the data pin
42
of the DUT
40
. The clock signal
120
is produced based on the reference clock RCLK and the tester rate signal
200
. The test pattern data
620
is produced based on the pattern data
600
with use of the reference clock RCLK
100
and the tester rate signal
200
.
The procedure for testing the DUT
40
having the PLL circuit
45
by the semiconductor test system of
FIG. 3
is explained with reference to the timing chart of FIG.
4
.
FIG. 4
is directed to a process for conducting a function test on the DUT. In general, the function test of an IC device under test is carried out by supplying the test pattern data which is divided into a large number of pattern blocks to the IC device. In
FIG. 4
, before the start of the function test, the PLL circuit
45
in the DUT
40
has to be brought to the lock end (phase lock state) by applying the clock signal
120
to the PLL circuit
45
.
In the arrangement of the conventional technology of
FIG. 3
, the clock signal
120
to the PLL circuit
45
stops when the tester rate signal
200
stops. If the clock signal is not supplied, the phase lock state in the PLL circuit
45
is destroyed (out of phase lock).
As stated above, in general, when a function test is performed for an IC device, the overall test pattern is separated into several hundred blocks to several thousand blocks of test patterns. Thus, the test patterns are generated continuously in the unit of several 10k patterns or several 100k patterns for each pattern block. Prior to the start of each of the blocks of test patterns, the clock signal
120
must be provided to the PLL circuit
45
to bring the PLL circuit
45
to the phase lock state. Since the PLL circuit
45
needs a certain length of time, such as several milliseconds, to reach the phase lock state (lock end) for each block of the test pattern, a significant amount of time is required to phase lock the PLL circuit to complete the function test.
This operational process in the conventio

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