Semiconductor test management system and method

Details Semiconductor test management system and method Semiconductor test management system and method

2007-06-26

2007-06-26

Brett, Cynthia (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C702S117000

Reexamination Certificate

active

10963863

ABSTRACT:
A system and method thereof for semiconductor test management. A first computer generates a new gating rule and transmits the new gating rule. A second computer receives the new gating rule via a network, acquires a test result, carries the test result into the new gating rule to generate an advisory report. In which, the test result comprises a test value corresponding to a test attribute, the new gating rule determines a final advisory when the test value satisfies a specific condition comprising the test attribute, and the advisory report comprises the final advisory.

REFERENCES:
patent: 4845843 (1989-07-01), Babcock
patent: 5355320 (1994-10-01), Erjavic et al.
patent: 6493425 (2002-12-01), Abe
patent: 6638779 (2003-10-01), Taira
patent: 2003/0229465 (2003-12-01), Kritt

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