Semiconductor substrate and land grid array semiconductor...

Details Semiconductor substrate and land grid array semiconductor... Semiconductor substrate and land grid array semiconductor...

2002-05-30

2004-01-27

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C438S124000, C438S126000, C257S778000

Reexamination Certificate

active

06682957

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor chip package, and more particularly to an improved semiconductor substrate and land grid array (hereinafter, referred to as “LGA”) type semiconductor chip package using the same and respective fabrication methods thereof.
2. Background of the Related Art
Recently, a quad flat package (hereinafter, referred to as “QFP”) is widely employed as a multi-pin package and allows the outer leads to become narrower in width and the pitches between respective leads to become smaller. However, such a structure causes the leads to easily bend. Further, when such a multi-pin package is mounted on a printed circuit board, an appropriate alignment and an adjustment of a soldering amount between the package and the printed circuit board are difficult. In order to overcome the disadvantages of QFP while satisfying the prevailing multi-pin package trend, a ball grid array (hereinafter, referred to as “BGA”) type semiconductor package has been developed. The BGA type semiconductor package employs solder balls which serve to substitute for outer leads, and overcomes the disadvantages of QFP.
As shown in
FIG. 1
, the BGA package includes a substrate
1
embedded by a plurality of patterned conductive interconnections (not shown). A semiconductor chip
2
is attached by an adhesive
3
onto the substrate
1
. The semiconductor chip
2
and the plurality of interconnections (not shown) embedded in the substrate
1
are electrically connected by corresponding ones of a plurality of conductive wires
4
. Also, the semiconductor chip
2
and the wires
4
are encapsulated by a molding compound
5
. A plurality of solder balls
6
disposed on the bottom surface of the substrate
1
are respectively connected to a corresponding one of the interconnections (not shown) embedded in the substrate
1
. Here, the respective interconnection (not shown) in the substrate
1
respectively serves as a channel which electrically links between the upper and lower surfaces of the substrate
1
.
However, the semiconductor chip of
FIG. 1
is completely sealed by the molding compound, and external heat dissipation from the semiconductor chip is difficult. Further, because the solder balls serving as input/output terminals for electrical signals are formed only on the bottom surface of the substrate, a multi-layer semiconductor package module is difficult to manufacture.
SUMMARY OF THE INVENTION
It is an object of the invention to overcome the problems of the related art.
Another object of the invention is to improve heat dissipation in chip packages.
A further object of the invention is to provide a laminated structure for a multi-layer semiconductor package module.
A further object of the invention is to improve solder joint reliability.
Accordingly, it is another object of the present invention to provide a semiconductor substrate for a semiconductor package and a land grid array (LGA) type semiconductor chip package using the same and respective fabrication methods thereof.
To achieve the above-described objects in a whole or in parts, the semiconductor substrate for a semiconductor package according to the present invention includes an insulation body having a plurality of first conductive interconnections embedded therein, a cavity formed in an upper central portion of the insulation body, a plurality of first conductive interconnection patterns formed outside the cavity and on each of the respective marginal upper surfaces of the insulation body, a plurality of second conductive interconnection patterns formed on each of the respective marginal lower surfaces of the insulation body, a plurality of third conductive interconnection patterns for electrically connecting the first and second conductive interconnection patterns, and a plurality of conductive bond pads formed on a bottom of the cavity.
Further, to achieve the above-described objects in a whole or in parts, the LGA (Land Grid Array) type semiconductor chip package includes an insulation body having a plurality of first conductive interconnections embedded therein, a cavity formed in an upper central portion of the insulation body, a plurality of first conductive interconnection patterns formed outside the cavity and on each of the respective marginal upper surfaces of the insulation body, a plurality of second conductive interconnection patterns formed on each of the respective marginal lower surfaces of the insulation body, a plurality of third conductive interconnection patterns for electrically connecting the first and second conductive interconnection patterns, a plurality of conductive bond pads formed on a bottom of the cavity, a semiconductor chip formed by a first adhesive member on the respective bond pads, a heat discharge member attached by a second adhesive member on an upper surface of the semiconductor chip, and an epoxy molding compound filled in the cavity.
Still further, to achieve the above-described objects in a whole or in parts, the substrate fabrication method for a semiconductor chip package according to the present invention includes the steps of forming an insulation body having a plurality of first conductive interconnections embedded therein, forming a plurality of cavities in upper central portions of the insulation body, forming a plurality of first conductive interconnection patterns outside the cavity and on each of the respective marginal upper surfaces of the insulation body, forming a plurality of second conductive interconnection patterns on each of the respective marginal lower surfaces of the insulation body, forming a plurality of through holes formed vertically through the first and second conductive interconnection patterns and the insulation body provided between the first and second conductive interconnection patterns, filling of the plurality of through holes with conductive material, forming a rectangular opening in the insulation body by removing respective outside portions of the conductive material filled in each of the through holes, and forming a plurality of conductive bond pads on each bottom of the cavities.
Also, to achieve the above-described objects in a whole or in parts, the substrate fabrication method for a semiconductor chip package according to the present invention includes the steps of forming an insulation body having a plurality of first conductive interconnections embedded therein, forming a plurality of cavities in upper central portions of the insulation body, forming a plurality of first conductive interconnection patterns outside the cavity and on each of the respective marginal upper surfaces of the insulation body, forming a plurality of second conductive interconnection patterns on each of the respective marginal lower surfaces of the insulation body, forming a plurality of through holes formed vertically through the first and second conductive interconnection patterns and the insulation body provided between the first and second conductive interconnection patterns, filling of the plurality of through holes with conductive material, forming a rectangular opening in the insulation body by removing respective outside portions of the conductive material filled in each of the through holes, forming a plurality of conductive bond pads on each bottom of the cavities, forming a semiconductor chip by a first adhesive member on the bond pads, forming a heat discharge member by a second adhesive member on an upper surface of the semiconductor chip, and filling an epoxy molding compound in the cavity.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.


REFERENCES:
patent: 5241133 (1993-08-01), Mullen, III et al.
patent: 5355283 (1994-10-01), Ma

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