Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-02-06
2008-07-29
Lee, Calvin (Department: 2892)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
07405142
ABSTRACT:
A semiconductor substrate manufacturing method has a first layer formation process, a second layer formation process, a heat treatment process, and a polishing process; in the first layer formation process, the thickness of the first SiGe layer is set to less than twice the critical thickness, which is the film thickness at which dislocations appear and lattice relaxation occurs due to increasing film thickness; in the second layer formation process, the Ge composition ratio of the second SiGe layer is at least at the contact face with the first SiGe layer or with the Si layer, set lower than the maximum value of the Ge composition ratio in the first SiGe layer, and moreover, a gradient composition region in at least a portion of which the Ge composition ratio increases gradually toward the surface is formed. By this means, the penetrating dislocation density is kept low, surface roughness is low, and worsening of roughness at the surface and at interfaces due to heat treatment in device manufacturing processes or similar is prevented.
REFERENCES:
patent: 5221413 (1993-06-01), Brasen et al.
patent: 5352912 (1994-10-01), Crabbe et al.
patent: 5442205 (1995-08-01), Brasen et al.
patent: 5500389 (1996-03-01), Lee et al.
patent: 6107653 (2000-08-01), Fitzgerald
patent: 6525338 (2003-02-01), Mizushima et al.
patent: 2002/0017642 (2002-02-01), Mizushima et al.
patent: 2002/0084000 (2002-07-01), Fitzgerald
patent: 1336684 (2002-02-01), None
patent: 101 37 369 (2002-04-01), None
patent: 0 541 971 (1993-05-01), None
patent: 06-177046 (1994-06-01), None
patent: 06-252046 (1994-09-01), None
patent: 07-193078 (1995-07-01), None
patent: 07-201734 (1995-08-01), None
patent: 2000-513507 (2000-10-01), None
patent: 2002-118254 (2002-04-01), None
patent: 2002-217413 (2002-08-01), None
patent: 2002-289533 (2002-10-01), None
patent: 2002-359188 (2002-12-01), None
patent: 2003-022970 (2003-01-01), None
patent: 2001-0014201 (2001-02-01), None
patent: 2002-0011338 (2002-02-01), None
patent: WO 98/00857 (1998-01-01), None
patent: WO 98/59365 (1998-12-01), None
patent: WO 03/015140 (2003-02-01), None
R. People et al., “Calculation of critical layer thickness versus lattice mismatch for GexSi1-x/Si strained-layer heterostructures”, Applied Physics Letters, vol. 47, No. 3, Aug. 1, 1985, pp. 322-324.
J. P. Dismukes, et al., “Lattice Parameter and Density in Germanium-SIlicon Alloys”, The Journal of Physical Chemistry, vol. 68, No. 10, Oct. 1964, pp. 3021-3027.
Kougami Hazumu
Ninomiya Masaharu
Shiono Ichiro
Lee Calvin
Pillsbury Winthrop Shaw & Pittman LLP
Sumco Corporation
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