Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-07-28
2001-05-01
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S408000
Reexamination Certificate
active
06225662
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed generally to semiconductor structures, and more particularly, to a semiconductor structure having a localized heavily doped buried region to control the location of a breakdown voltage, or having a heavily doped buried region that in part, surrounds a device, thereby preventing latch-up or serving as a collector region.
BACKGROUND OF THE INVENTION
Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applicability and numerous disciplines. One such siliconbased semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
The principal elements of a typical MOS semiconductor device are illustrated in FIG.
1
. The device
100
generally includes a gate electrode
103
of doped polycrystalline silicon, which acts as a conductor, to which an input signal is typically applied via a gate terminal
104
. Heavily doped source and drain regions
105
and
106
are formed in a semiconductor substrate
101
and are respectively connected to source and drain terminals
107
and
108
. A channel region
109
is formed in the semiconductor substrate
101
, which is often referred to as the body region of the transistor, beneath the gate electrode
103
that separates the source and drain regions
105
and
106
when the appropriate voltage is applied to the gate. The body region is typically lightly doped with a dopant type opposite to that of the source/drain regions
105
. The gate electrode
103
is physically separated from the semiconductor substrate
101
by a gate insulating layer
110
, typically an oxide layer such as SiO
2
. The insulating layer
110
is provided to prevent current from flowing between the gate electrode
103
and the source and drain regions
105
and
106
, the body region
101
, or the channel region
109
. A body contact region
112
that is heavily doped with a dopant opposite that of the source and drain regions
105
and
106
is also formed to connect the body region to a voltage. The body contact region
112
is connected to a grounded body terminal
114
, for example.
In operation, an output voltage is typically developed between the source and drain terminals
107
and
108
. When the correct input voltage is applied to the gate electrode
103
, the electric field below the gate
103
induces the channel region
109
. By varying the voltage on the gate
103
, and hence the electric field, it is possible to modulate the conductance of the channel region
109
between the source and drain regions
105
and
106
. In this manner an electric field controls the current flow through the channel region
109
. This type of device is commonly referred to as a MOS field-effect-transistor (MOSFET).
The ability of both n-channel and p-channel MOSFETs to withstand over-voltage conditions is important for device reliability. MOSFETs connected to input or output pads are most likely to experience an over-voltage condition. If the drain-to-source breakdown voltage (BV
dss
) of a MOS transistor is exceeded, the resulting current flow may damage or destroy the device. In
FIG. 1
, the drain is reverse biased and the resulting depletion region
120
extends under the gate
103
.
Damage can be caused by breakdown occurring at or near the surface of the transistor. The device can be damaged in two ways. First, energetic electrons and holes that are generated when breakdown occurs can be injected into the dielectrics in the vicinity of the drain-to-body junction, particularly the gate dielectric
110
, thereby changing the apparent threshold voltage of the MOSFET. The change in apparent threshold voltage can result in a higher current flow for the same applied gate voltage, which can destroy a transistor if the reduction in the apparent threshold voltage is sufficiently large. Second, heat that is generated near the surface as a result of the localized power dissipation can alter the characteristics of the materials in the area, for example, silicon, metals, and dielectrics. Increased conductivity can result and change the performance of the MOSFET.
Therefore, a semiconductor structure that addresses the above identified problems associated with drain-to-body breakdown is desirable.
SUMMARY OF THE INVENTION
A semiconductor structure is provided that controls the location and value of breakdown for various types of devices. In a first embodiment, a semiconductor is provided that comprises a substrate of a first type and having a surface. A source region is disposed in the substrate at the surface and is doped with dopant of a second type. A drain region is disposed in the substrate at the surface and doped with dopant of the second type, and a gate structure is disposed on the substrate between the source and drain regions. A breakdown region is disposed in the substrate below the drain region and is heavily doped with dopant of the first type to control the value and location of breakdown.
A method for making a semiconductor structure is provided in another embodiment. The method comprises forming a substrate of a first type, and implanting a first heavily doped breakdown region in the substrate with a dopant of the first type. A source region is implanted in the substrate with dopant of a second type, and a drain region is implanted in the substrate above the breakdown region with dopant of the second type. A gate structure is formed on the substrate between the source and drain regions.
A semiconductor structure that protects against latch-up is provided in another embodiment. The structure comprises a substrate of a first type, a source region disposed in the substrate and doped with dopant of a second type, and a drain region disposed in the substrate and doped with dopant of the second type. A gate structure is disposed on the substrate between the source and drain regions, and a breakdown region is disposed in the substrate below the source and drain regions. The breakdown region is heavily doped with dopant of the first type and coupled to a surface of the substrate with a heavily doped body contact region.
A bipolar semiconductor structure is provided in another embodiment of the invention. The structure comprises a substrate of a first dopant type; an emitter region disposed in the substrate and doped with a dopant of a second type; a base contact region disposed in the substrate and doped with dopant of the first type; and a collector region disposed in the substrate below and surrounding the emitter and base regions, heavily doped with dopant of the second type.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.
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Wolf et al., Silicon Processing for the VLSI Era vol. 1: Process Technology, Lattice Press, pp. 290, 325, 1986.
Crawford PLLC
Loke Steven
Philips Semiconductors Inc.
Tran Thien F.
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