Semiconductor structure including laminated isolation region

Details Semiconductor structure including laminated isolation region Semiconductor structure including laminated isolation region

2007-03-13

2008-07-01

Wilczewski, M. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S222000, C438S300000, C438S435000

Reexamination Certificate

active

07393751

ABSTRACT:
A semiconductor structure and a related method for fabrication thereof include an isolation region located within an isolation trench within a semiconductor substrate. The isolation region comprises; (1) a lower lying dielectric plug layer recessed within the isolation trench; (2) a U shaped dielectric liner layer located upon the lower lying dielectric plug layer and partially filling the recess; and (3) an upper lying dielectric plug layer located upon the U shaped dielectric liner layer and completely filling the recess. The isolation region provides for sidewall coverage of the isolation trench, thus eliminating some types of leakage paths.

REFERENCES:
patent: 6133105 (2000-10-01), Chen et al.
patent: 6277709 (2001-08-01), Wang et al.
patent: 6465325 (2002-10-01), Ridley et al.
patent: 6878606 (2005-04-01), Ohnish et al.
patent: 7033909 (2006-04-01), Kim et al.
patent: 7135371 (2006-11-01), Han et al.
patent: 7193271 (2007-03-01), Lee et al.
patent: 2003/0013272 (2003-01-01), Hong et al.
patent: 2003/0234433 (2003-12-01), Tran
patent: 2004/0072408 (2004-04-01), Yun et al.
patent: 2005/0009293 (2005-01-01), Kim et al.
patent: 2005/0266647 (2005-12-01), Kim et al.
patent: 2006/0131665 (2006-06-01), Murthy et al.
patent: 2006/0148196 (2006-07-01), Thean et al.
patent: 2007/0020879 (2007-01-01), Baek et al.
Quirk et al., “Silicon and Wafer Preparation”, Semiconductor Manufacturing Technology, Prentice Hall, 2001 (pp. 87-88).

Affiliated with

Also associated with

Rating

Semiconductor structure including laminated isolation region does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor structure including laminated isolation region, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor structure including laminated isolation region will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3968119