Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate
Reexamination Certificate
2007-06-19
2007-06-19
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
C257S192000
Reexamination Certificate
active
11280336
ABSTRACT:
A method for fabricating a semiconductor structure having a high-strained crystalline layer with a low crystal defect density is disclosed. The structure includes a substrate having a first material comprising germanium or a Group(III)-Group(V)-semiconductor or alloy thereof. In addition, a crystalline epitaxial first layer, comprising a graded buffer layer and a substantially relaxed layer, is provided. The buffer layer is sufficiently relaxed to provide relaxation of the substantially relaxed layer deposited thereon. A further layer may be provided on the first layer, and the transfer of at least the further layer is facilitated by providing a weakened zone in the first layer.
REFERENCES:
patent: 5770868 (1998-06-01), Gill et al.
patent: 6039803 (2000-03-01), Fitzgerald et al.
patent: 6059895 (2000-05-01), Chu et al.
patent: 6916727 (2005-07-01), Leitz et al.
patent: 2002/0017642 (2002-02-01), Mizushima et al.
patent: 2002/0084000 (2002-07-01), Fitzgerald
patent: 2002/0100942 (2002-08-01), Fitzgerald et al.
patent: 2002/0125475 (2002-09-01), Chu et al.
patent: 2002/0167048 (2002-11-01), Tweet et al.
patent: 2005/0009288 (2005-01-01), Cheng et al.
patent: 2005/0054171 (2005-03-01), Chu et al.
patent: 1364309 (2001-03-01), None
patent: 1388589 (2003-01-01), None
patent: 1 197 992 (2002-04-01), None
patent: 1 253 648 (2002-10-01), None
patent: 512487 (2002-12-01), None
patent: WO 02/15244 (2002-02-01), None
T. Asano et al., “Structrual characterization of Si1-xGexalloy layers grown by molecular beam epitaxy on Si(001) substrates,” Journal of Applied Physics, vol. 87, No. 12 (2000) 8759-8765.
Z. Cheng et al., “SiGe-on-Insulator (SGOI): Substrate Preparation and MOSFET Fabrication for Electron Mobility Evaluation,” 2001 IEEE International SOI Conference, Oct. 2001, 13-14.
J.P. Colinge, “Silicon-on-Insulator Technology,” VLSI, p. 47.
B. Gallas et al., “Influence of misfit and threading dislocations on the surface morphology of SiGe graded-layers,” Journal of Crystal Growth 201/202 (1999) 547-550.
L. Huang et al., “Electron and hole mobility enhancement in strained SOI by wafer bonding,” IEEE Transactions on Electron Devices, vol. 49, No. 9, (2002) 1566-1571.
“Silicon Wafer Bonding Technology,” S.S. Iyer & A.J. Auberton-Herve (ed.), EMIS Processing Series No. 1, pp. 22, 36, 57.
Li et al., “Investigation of strain relaxation of Ge1-xSixepilayers on Ge(001) by high-resolution x-ray reciprocal space mapping,” Semiconductor Science and Technology, vol. 10 (Dec. 1995) 1621-1628.
D. Paul, “The Physics, Material and Devices of Silicon Germanium Technology,” Physics World, pp. 1-14.
S. Takagi et al., “Device structure and electrical characteristics of strained-Si-on-insulator (strained-SOI) MOSFETs,” Material Science and Engineering, B89 (2002) 426-434.
G. Taraschi et al., “Relaxed SiGe-on-insulator fabricated via wafer bonding and etch back,” J. Vac. Sci. Technol., B 20(2) (Mar./Apr. 2002) 725-727.
Aulnette Cécile
Dupont Frederic
Mazure Carlos
S.O.I.Tec Silicon on Insulator Technologies S.A.
Winston & Strawn LLP
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