Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-05-26
2001-09-11
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S230030
Reexamination Certificate
active
06288958
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor storage devices, and more particularly to semiconductor storage devices that include a plurality of different memory types.
BACKGROUND OF THE INVENTION
Many semiconductor memory devices typically include memory cells of one type. Such semiconductor memory devices may include one or more arrays of one type of memory cell (e.g., dynamic random access memory (DRAM) cells). However, semiconductor memory devices may also have two or more memory sections, where each of which may contain a different memory type.
To improve quality and reliability, semiconductor memory devices may be subject to a “burn-in” test. A burn-in test can be a type of screening that operates a device at a high temperature, typically about 125° C. Such a higher temperature can accelerate latent defects, thus detecting devices that may initially operate normally, but subsequently fail over time.
Conventionally a burn-in test can follow the normal operation of a semiconductor device. Consequently, in a semiconductor memory device that includes two or more memory sections, only one memory section is tested at a time. Thus, a burn-in test for such devices can switch between memory sections, stressing only one individual memory section at a time. As a result, the more memory sections a semiconductor device includes, the longer a burn-in test may take. Longer burn-in tests can slow manufacturing throughput and/or increase testing costs.
To better understand the present invention, a conventional semiconductor storage device having two memory sections, and a corresponding normal and burn-in test mode will now be described. Referring now to
FIG. 5
, a conventional semiconductor storage device is shown that includes two memory sections, a random access memory (RAM) section
10
and a read-only-memory section
20
. Herein, a RAM section
10
will be referred to as a first memory section and a ROM section
20
will be referred to as a second memory section. The first and second memory sections (
10
and
20
) may include respective memory cell arrays, and peripheral circuits that may receive and decode an applied address to access memory cells within each memory section (
10
and
20
).
FIG. 5
is shown to particularly include a first memory section (RAM)
10
that includes a first memory cell array
11
, a first address buffer
12
, a first address decoder
13
, a first X decoder
14
, a first Y selector
15
, and a first sense amplifier
16
. Similarly, a second memory section (ROM)
20
may include a second memory cell array
21
, a second address buffer
22
, a second address decoder
23
, a second X decoder
24
, a second Y selector
25
, and a second sense amplifier
26
.
An address, represented as AD0, AD1 . . . , can be supplied to first and second address buffers (
12
and
22
). First and second address buffers
12
and
22
can be connected to first and second address decoders
13
and
23
, respectively. First address decoder
13
may be connected to first X decoder
14
and first Y selector
15
. Second address decoder
23
may be connected to second X decoder
24
and second Y selector
25
. The first X decoder
14
and Y selector
15
may be connected to first memory cell array
11
, while second X decoder
24
and Y selector
25
may be connected to second memory cell array
21
. A first memory cell array
11
may be connected to first sense amplifier
16
and second memory cell array
21
may be connected to second sense amplifier
26
.
The conventional semiconductor storage device of
FIG. 5
may also include a write enable (W/E) circuit
30
, a first selection circuit
41
′ and a second selection circuit
42
′. A W/E circuit
30
may place a first memory section
10
in a write mode. In
FIG. 5
, a W/E circuit
30
may be connected to a first sense amplifier
16
and a common input/output (I/O) buffer circuit
50
.
A first selection circuit
41
′ may be connected to a memory section selection pin (pin
0
′) and can activate or deactivate a first memory section
10
, while a second selection circuit
42
′ may be connected to a second selection pin (pin
1
′) and can activate or deactivate a second memory section
20
.
In operation, a first selection circuit
41
′ may provide a first chip selection signal CE
10
to a first address buffer
12
by way of a first inverter
46
. A second selection circuit
42
′ may provide a second chip selection signal CE
20
by way of a second inverter
47
. First and second selection circuits (
41
′ and
42
′) can also be connected to common I/O buffer circuit
50
A common I/O buffer circuit
50
can serve to reduce the number of external I/O pins necessary for outputting and/or inputting data to the first or second memory sections (
10
and
20
).
As noted above, a typical conventional burn-in test for a semiconductor storage device can be conducted while the semiconductor storage device is operating in a normal manner. Thus, for a semiconductor storage device such as that shown in
FIG. 5
, one of the memory sections (
10
or
20
) can be selected by providing a particular logic value (e.g., a low logic value) as an input to a first selection circuit
41
′ or a second selection circuit
42
′.
By way of example, assume that a low logic value is supplied as an input to first selection circuit
41
′ at memory section selection pin
0
′. A low pin
0
′ value can result in the first chip section selection CE
10
being active (e.g., high). An active CE
10
signal can select the first memory section
10
.
Next, assume that a low logic value is supplied to as an input to the second selection circuit at memory selection pin
1
′. In this case, a low pin
1
′ value can result in the second chip section selection CE
20
being active (e.g., high). An active CE
20
signal can select the second memory section
20
.
If both first and second selection pins (pin
0
′ and pin
1
′) receive inactive levels (e.g., high), both first and second memory sections (
10
and
20
) can be disabled.
However, if both first and second selection pins (pin
0
′ and pin
1
′) receive active levels, both first and second memory sections (
10
and
20
) can be enabled. Such a state is not desirable in a normal mode of operation as first and second memory sections (
10
and
20
) can share a common I/O buffer circuit
50
, and multiple data sets could arrive at the same time providing invalid results. For these reasons, conventional semiconductor storage devices that follow normal modes of operation during a burn-in test have activated only a first or second memory section (
10
and
20
) in such a burn-in test.
As noted above, in the normal operation of a conventional semiconductor storage device, first and second memory sections are not activated simultaneously. Thus, because a burn-in test can follow a normal operating procedure, burn-in tests can be conducted as shown in FIG.
6
A.
FIG. 6A
shows access to memory cells during a burn-in test in a conventional semiconductor storage device. As shown in
FIG. 6A
, initially a low value is applied to memory section selection pin
0
′ and a high value is applied to memory section selection pin
1
′ to access a first memory section
10
. Subsequently, a high value is applied to memory section selection pin
0
′ and a low value is applied to memory section selection pin
1
′ to access a second memory section
20
. Such an arrangement can increase test times, as each memory section (
10
and
20
) is activated one after the other.
Various other conventional approaches related to the present invention are known. Japanese Patent Laid-Open No. 6-84396 (hereinafter referred to as “prior art
1
”), describes a semiconductor storage device designed to reduce a dynamic bias test time (BT). In prior art
1
, a semiconductor storage device can include multiple memory sections. When a test signal is inactive, one section selection signal can be activated according
Dinh Son T.
NEC Corporation
Walker Darryl G.
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