Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2006-09-15
2008-09-16
Nguyen, VanThu (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189020, C365S219000, C365S233100
Reexamination Certificate
active
07426144
ABSTRACT:
A semiconductor storage device comprising: a transfer control circuit for prefetching data of a predetermined number of bits stored in a memory array in response to a read command, and transferring L bits of the prefetched data in parallel to an internal bus in synchronization with an internal clock; and an output buffer circuit which includes L FIFO buffers each for latching each bit of the L bits input from the internal bus and extracts stored data from each of the L FIFO buffers in accordance with an input sequence in synchronization with an external clock so as to transfer the data serially to outside, wherein each of the L FIFO buffers includes an M-bit latch circuit and an N-bit latch circuit, and paths of the M-bit and N-bit latch circuits can be selectively switched.
REFERENCES:
patent: 5999458 (1999-12-01), Nishimura et al.
patent: 6914829 (2005-07-01), Lee
patent: 2001-243770 (2001-09-01), None
Elpida Memory Inc.
McDermott Will & Emery LLP
Nguyen Van-Thu
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