Semiconductor storage device

Details Semiconductor storage device Semiconductor storage device

2006-06-13

2006-06-13

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000, C365S203000

Reexamination Certificate

active

07061788

ABSTRACT:
A semiconductor storage device comprises first and second memory cells, each connected to the first pair of word line and bit line and a second pair of word line and bit line, a sense amplifier connected between the first and second bit lines, a first capacitor whose storage electrode being connected to the first bit line, a second capacitor whose storage electrode being connected to the second bit line, first and second wires respectively connected to the first and second plate electrodes of the first and second capacitors, wherein the first and second bit lines are in a complementary relation, and when “0” is read to the first bit line, the first capacitor has an operation to increase a potential of the first plate electrode through the first wire before the sense amplifier operates.

REFERENCES:
patent: 6026009 (2000-02-01), Choi et al.
patent: 6392916 (2002-05-01), Choi et al.
patent: 6510071 (2003-01-01), Oowaki
patent: 2000-339973 (2000-12-01), None
patent: 2002-216498 (2002-08-01), None
Ryu Ogiwara, et al. “A 0.5-μm, 3-V, 1T1C, 1-Mbit FRAM with a Variable Reference Bit-Line Voltage Scheme Using a Fatigue-Free Reference Capacitor”, IEEE Journal of Solid-State Circuits, vol. 35, No. 4, Apr. 2000, pp. 545-551.
Daisaburo Takashima, et al. “High-Density Chain Ferroelectric Random Access Memory (Chain FRAM)”, IEEE Journal of Solid-State Circuits, vol. 33, No. 5, May 1998, pp. 787-792.
Shoichiro Kawashima, et al. “Bitline GND Sensing Technique for Low-Voltage Operation FeRAM”, IEEE Journal of Solid-State Circuits, vol. 37, No. 5, May 2002, pp. 592-598.
Ryu Ogiwara, et al. “A 0.5-um, 3-V, 1T1C, 1-Mbit FRAM with a Variable Reference Bit-Line Voltage Scheme Using a Fatigue-Free Reference Capacitor”, IEEE Journal of Solid-State Circuits, vol. 35, No. 4, Apr. 2000, pp. 545-551.
Daisaburo Takashima, et al. “High-Density Chain Ferroelectric Random Access Memory (Chain FRAM)”, IEEE Journal of Solid-State Circuits, vol. 33, No. 5, May 1998, pp. 787-792.
Shoichiro Kawashima, et al. “Bitline GND Sensing Technique for Low-Voltage Operation FeRAM”, IEEE Journal of Solid-States Circuits, vol. 37 No. 5, May 2002, pp. 592-598.

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