Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2000-12-19
2002-04-02
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S225700, C365S230030, C365S201000
Reexamination Certificate
active
06366503
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor storage devices, and more particularly to semiconductor storage devices having selectable input and/or output bit configurations.
BACKGROUND OF THE INVENTION
Typically, a semiconductor storage device can receive input data and provide output data as a series of bits, most often in parallel. Different applications or users may have a desire for different input/output (I/O) bit widths. That is, while one application may desire an 18 bit (x18) I/O configuration, another might desire a 36 bit (x36) I/O configuration.
To take advantage of manufacturing in scale, in many cases the same basic semiconductor storage device design can be used for devices having different I/O configurations. Such an arrangement can be more economical, efficient and/or reliable than producing one design having one I/O configuration (e.g., x18), and producing another design having another I/O configuration (e.g., x36).
One conventional approach to selecting (or switching) between I/O configurations can include different wiring schemes. As but one example, Japanese Patent Application Laid-Open No. Hei 8-315578 discloses a semiconductor storage device which includes a memory cell array composed of a number of memory blocks, an I/O selecting section for selecting certain bit structures from a number of such bit structures, and a data selecting section for receiving an output signal from the I/O selecting section and switching the number of data inputs and data outputs.
FIG. 2
of the above-identified publication shows a structure that may be switched between a x18 and a x36 I/O configuration. In the structure shown, 36 data buses are provided in parallel. The 36 data buses can correspond to the x36 I/O configuration. Two data signal lines, that may be switched, are commonly connected to each data bus. In a x36 I/O configuration, the two signal lines commonly connected to the same data bus may be separated from one another resulting in one signal line being connected to one data bus. Data may then be input and output by way of data I/O circuits and the 36 data buses. In contrast, in a x18 I/O configuration, one of the two data signal lines commonly connected to the same data bus can be selected by the data selecting section. As a result, 18 of the data buses are used. Data may then be input and output by way of data I/O circuits and the 18 data buses.
In conventional approaches, such as that described above, data buses can be arranged in parallel. As the bit widths of semiconductor storage devices continues to grow, it can be difficult to accommodate larger and larger data buses on an integrated circuit. In addition, within a memory cell array region, a data selecting section can be included for each data signal line, to enable switching between the various I/O configurations (e.g., x36 and x18). Consequently, the number of circuit elements increases for such approaches. Increased circuit elements can increase overall memory size and/or complicate a design.
Conventional approaches may have further drawbacks. In many cases, the selection between I/O configurations can be accomplished by way of a mask change. As is well known in the art, a semiconductor storage device may be manufactured with a series of masks for patterning various layers. One conventional way of switching between I/O configurations can be done by changes between the sets of mask patterns for some interconnect layers, such as an aluminum wiring layer. Manufacturing such masks can be expensive. Further, layers, such as aluminum wiring layers, have to be changed in the fabrication process to accomplish switching between I/O configurations. Therefore, market demands for each I/O configuration have to be precisely estimated several months before the material is shipped. Thus, conventional masking approaches to I/O configurations are not always feasible in meeting rapidly changing demands for each I/O configuration.
In light of the above discussion, it would be desirable to arrive at a semiconductor storage device that includes selectable I/O configurations, while at the same time does not include as many parallel data bus lines or circuit elements as conventional approaches.
It would also be desirable to arrive at a memory device with selectable I/O configurations that may be switched to one particular I/O configuration more rapidly than conventional approaches.
SUMMARY OF THE INVENTION
According to the present invention, a semiconductor storage device that is selectable between at least two input/output (I/O) configurations may include a number of data buses that can be arranged in parallel. Each data bus may be separated into at least two sections by a disconnecting circuit. In one I/O configuration, the data buses are separated by the disconnecting circuits. In another I/O configuration, the data bus sections are joined by the disconnecting circuits.
According to one aspect of the present invention, a disconnecting circuit may include a transistor, more particularly an insulated gate field effect transistor, even more particularly an n-channel insulated gate field effect transistor.
According to one aspect of the present invention, a disconnecting circuit may include a fuse, more particularly a metal fuse, even more particularly a fuse comprising aluminum. A fuse may be formed from a wiring layer and have a line thickness less than other wiring lines. Such a fuse may be formed below a window in an insulating layer and can be openable by laser irradiation. In addition, or alternatively, a fuse may be formed below an insulating layer and connected to a wiring layer by holes through the insulating layer. Such a fuse can be openable by running current through the fuse by way of the wiring layer. The fuses of the data buses may be aligned with one another in one direction and/or offset from one another with respect to one direction.
According to another aspect of the invention, data buses may be separable into first portions and second portions. A semiconductor storage device may further include I/O circuits for accessing data buses. I/O circuits may include first I/O circuits coupled to the first portions of the data buses and second I/O circuits coupled to the second portions of the data buses. In one I/O configuration (e.g., x36), all of the I/O circuits may be activated. In another I/O configuration (e.g., x18), less than all of the first I/O circuits and less than all of the second I/O circuits may be activated.
According to another aspect of the embodiments, a semiconductor storage device may include first and second memory cell arrays. N sense amplifiers may be connected to the first memory cell array and N sense amplifiers may be connected to the second memory cell array. N I/O circuits may correspond to the N sense amplifiers connected to the first memory cell array, and N I/O circuits may correspond to the N sense amplifiers connected to the second memory cell array.
REFERENCES:
patent: 5708618 (1998-01-01), Toda et al.
patent: 6163062 (1998-12-01), Shiratake et al.
patent: 6088284 (2000-07-01), Lee et al.
patent: 6094387 (2000-07-01), Mine et al.
patent: 356090497 (1981-07-01), None
patent: 8-315578 (1996-11-01), None
Lam David
NEC Corporation
Nelms David
Walker Darryl G.
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