Semiconductor storage device

Details Semiconductor storage device Semiconductor storage device

2000-01-18

2001-01-30

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

Reexamination Certificate

active

06181620

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor storage device including a dynamic random access memory circuit and the like, and more particularly, it relates to a semiconductor storage device comprising memory cells each including two transistors and one storage capacitor.
A low latency DRAM cell of a dual word line and dual bit line system disclosed in U.S. Pat. Nos. 5,856,940, 5,963,468 and 5,963,497, in which each memory cell is provided with two transistors and one storage capacitor and is connected with two word lines and two bit lines, will now be described with reference to a drawing.
FIG. 7
shows the circuit configuration of a memory cell of a semiconductor storage device including the conventional low latency DRAM cell. The memory cell
10
of
FIG. 7
includes, for example, a first switch transistor
102
that is connected with a first word line WL
0
A at its gate, with a first bit line BL
0
A at its drain and with a storage node
101
at its source; a source switch transistor
103
that is connected with a second word line WL
0
B at its gate, with a second bit line BL
0
B at its drain and with the storage node
101
at its source; and a storage capacitor
104
that is connected with the storage node
101
at one electrode and uses a cell plate as the other electrode.
In this manner, the memory cell
100
includes the first switch transistor
102
and the second switch transistor
103
independently controllable with respect to one storage capacitor
104
. Accordingly, an interleaving operation can be conducted between a combination of the first word line WL
0
A and the first bit line BL
0
A and a combination of the second word line WL
0
B and the second bit line BL
0
B all extending over plural memory cells
100
, resulting in rapid read and write operations.
In the semiconductor storage device including the conventional low latency DRAM cells, however, the interleaving operation is conducted on bit lines adjacent to each other. Therefore, when first bit lines BLnA and second bit lines BLnB (wherein n is 0 or a larger integer) are operated independently of each other, a coupling noise derived from change of a bit line potential caused during the operation can be disadvantageously introduced into an adjacent bit line. In the worst case, the introduction of such a coupling noise can cause inversion of a data value held by the memory cell
100
.
SUMMARY OF THE INVENTION
The invention was devices to overcome the aforementioned conventional problem, and an object of the invention is, in a semiconductor storage device comprising memory cells each including two transistors and one capacitor, preventing an interference noise caused in one bit line from being introduced into an adjacent bit line.
In order to achieve the object, in the semiconductor storage device according to this invention, while a precharge signal or a sense amplifier activating signal of one bit line system is being kept in an active state, a precharge signal or a sense amplifier activating signal of the other bit line system is placed in an inactive state.
Specifically, the semiconductor storage device of this invention comprises plural memory cells each including a first switch transistor and a second switch transistor connected with each other through sources thereof and a storage capacitor for data storage connected with the sources of the transistors at one electrode thereof; plural first bit lines each connected with a drain of the first switch transistor of each of the memory cells; plural second bit lines each connected with a drain of the second switch transistor of each of the memory cells and disposed alternately with the plural first bit lines; plural first sense amplifiers respectively connected with the plural first bit lines; and plural second sense amplifiers respectively connected with the plural second bit lines, and in a period when a first precharge signal for precharging each of the plural first bit lines or a first sense amplifier activating signal for activating each of the plural first sense amplifiers is kept in an active state, a second precharge signal for recharging each of the plural second bit lines and a second sense amplifier activating signal for activating each of the plural second sense amplifiers are both placed in an inactive state.
In the semiconductor storage device of this invention, in the case where a data held in a memory cell is read from, for example, a second bit line, the second precharge signal applied to the second bit line is turned off, and the second switch transistor is then activated, so that charge stored in the storage capacitor can flow into the second bit line. In general, the second sense amplifier is not driven at this point because the second sense amplifier activating signal is in an inactive state. At this point, in the storage device of this invention, the first precharge signal or the first sense amplifier activating signal applied to a first bit line adjacent to the second bit line is kept in an active state. Accordingly, when the first precharge signal is kept at a high level and the first sense amplifier activating signal is kept at a low level, the first bit line is precharged to be placed in a low-impedance state. Therefore, even when the second sense amplifier activating signal thereafter undergoes a low to high transition so as to activate the second sense amplifier, the first bit line in a low-impedance state can work as a shield line.
Furthermore, when the first precharge signal is kept at a low level and the first sense amplifier activating signal is kept at a high level, the potential of the first bit line is defined as a high or low level so as to be place din a low-impedance state. Therefore, even when the second sense amplifier activating signal thereafter undergoes a low to high transition so as to activate the second sense amplifier, the first bit line in a low-impedance state can work as a shield line. As a result, a noise caused in the second bit line whose potential is changed due to a write operation can be prevented from being introduced into the other adjacent second bit line. Thus, the operation of the storage device can be stabilized.
In the semiconductor storage device of this invention, it is preferable that transition of the first sense amplifier activating signal from an active state to an inactive state, transition of the second precharge signal from an active state to an inactive state, and transition of the second sense amplifier activating signal from an inactive state to an active state are triggered in response to an edge of a clock signal for synchronizing operation of the semiconductor storage device. Further, in this case, it is preferable that transition of the first precharge signal from an inactive state to an active state is also triggered in response to the edge of the clock signal. At this point, for example, in a storage device having a configuration where the first precharge signal and the first sense amplifier activating signal are changed at one operation timing of the clock signal for synchronization and the second precharge signal and the second sense amplifier activating signal are changed at the other operating timing of the clock signal, and relative timing of changing the first precharge signal and the second sense amplifier activating signal is shifted when the cycle of the clock signal for synchronization is changed. Therefore, the first precharge signal can be unpreferably changed when the second precharge signal and the second sense amplifier activating signal are in an inactive state. According to the invention, however, since the first precharge signal and the second sense amplifier activating signal are changed at one operation timing of the clock signal for synchronization, the relative timing of changing the first precharge signal and the second sense amplifier activating signal can be avoided from being shifted even when the cycle of the clock signal is changed. Accordingly, the first precharge signal is never changed when the second precharge sig

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