Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1994-06-28
1997-01-21
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Bad bit
3652257, 36523006, 36518509, G11C 700, G11C 800
Patent
active
055965350
ABSTRACT:
A semiconductor storage device equipped with redundant circuits designed to increase the operating speed and to simplify the layout by providing for the detection of the storage of a faulty address and access to the faulty address so as to substitute a spare word line for a faulty word line. The semiconductor storage device includes a MOSFET for causing current to flow through a pair of fuse means by a complementary address signal at one end of a fuse means corresponding to each bit of the faulty address. The other end thereof is connected to a wired OR logic so as to generate a decision signal. The fuse means corresponding to the MOSFET which is turned on by the faulty address signal is cut off to store a faulty address. The faulty address storage and comparison units can be formed with the pair of fuses and the MOSFET. High-speed operation and a high-density layout in the form of a matrix can thus be achieved efficiently by switching the faulty circuit to a spare circuit while the normal decoder is operating.
REFERENCES:
patent: 5140554 (1992-08-01), Schreck et al.
patent: 5282165 (1994-01-01), Miyake et al.
patent: 5293339 (1994-05-01), Suzuki et al.
patent: 5293564 (1994-03-01), Sukegawa et al.
patent: 5337278 (1994-08-01), Cho
patent: 5375090 (1994-12-01), Yoshida
Kawamura Masayasu
Mushya Tathunori
Sukegawa Shunichi
Bassuk Lawrence J.
Donaldson Richard L.
Hiller William E.
Nelms David C.
Phan Trong
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