Semiconductor storage device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S768000, C714S774000

Reexamination Certificate

active

08074144

ABSTRACT:
Plural data lines read normal data stored in a first area in the memory cell array when the data lines are connected to a selected bit line. Plural parity data lines read parity data from a second area in the memory cell array different from the first area, the parity data being used for an error correction of the normal data stored in the memory cell. A first determination circuit compares the normal data read from the data lines and their expectation value, respectively, and determines whether the data and the expectation value coincide, respectively. A second determination circuit compares the parity data read from the parity data lines and their expectation value, respectively, and determines whether the data and the expectation value coincide, respectively. The second determination circuit includes a selection circuit that selectively outputs a determination result on a part of the parity data lines.

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Office Action issued Aug. 31, 2011 in Taiwanese Application No. 096130199 filed Aug. 15, 2007 (w/English translation).

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