Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2003-06-13
2004-11-30
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230030, C365S230060, C365S230080
Reexamination Certificate
active
06826091
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor storage apparatus. More particularly, the present invention relates to a semiconductor storage apparatus, in which data writing latch circuits are connected to bit lines in a memory cell array; groups consisting of the latch circuits and groups consisting of memory cells in columns in the memory cell arrays are divided into a plurality of areas in a row direction, and the plurality of latch circuits in each of the areas are connected to individual data lines.
A conventional semiconductor storage apparatus has been configured so that data writing latch circuits are provided on bit lines, for performing a latching operation at predetermined times (i.e., the total number of latch circuits divided by the number of data lines), and a writing operation is performed at the same time after data is set in all of the latch circuits. Here, the total number of latch circuits for simultaneously performing the writing operation is referred to as “one page”.
Hereinafter in
FIGS. 1-6
, “PL” denotes a latching operation, “Program” denotes a data transferring and writing operation, “PV” denotes a verifying operation, and “WAIT” denotes an operation standby. Furthermore, the numeral following “PL,” “Program,” and
The prior art is described below in reference to the drawings.
FIG. 6A
is a circuit diagram illustrating a semiconductor storage apparatus in the prior art; and
FIG. 6B
is a flowchart illustrating its operation.
In
FIG. 6A
, reference numeral
600
represents an area
0
obtained by division in the case of four data lines;
610
, an area
1
in the same manner;
601
to
604
, memory cells within the area
0
(
600
);
605
to
608
, data writing latch circuits within the area
0
(
600
);
611
to
614
, memory cells within the area
1
(
610
);
615
to
618
, data writing latch circuits within the area
1
(
610
);
620
, a word line;
621
, a data line for setting data in the latch circuits
605
to
608
within the area
0
(
600
); and
622
, a data line for setting data in the latch circuits
615
to
618
within the area
1
(
610
).
The operation of the semiconductor storage apparatus in the prior art configured as described above is explained below in accordance with the flowchart illustrated in FIG.
6
B. In the flowchart illustrated in
FIG. 6B
, the operations in the areas correspond to each other timewise.
First of all, writing data in the area
0
(
600
) is stored in the latch circuits
605
to
608
(STEP
0
).
Next, writing data in the area
1
(
610
) is stored in the latch circuits
615
to
618
(STEP
1
).
In this manner, latch setting of one page is completed.
Subsequently, the word line
620
is set to a predetermined writing voltage level. Thereafter, a verifying operation and a writing operation are repeated until all of the memory cells
601
to
604
and
611
to
614
have reached a predetermined threshold level (STEP
2
to STEP
5
).
With the above-described configuration, the parallelism of writing times is great, thereby achieving the writing operation at a relatively high speed.
However, with the above-described configuration, the writing operation is not started until the latch setting of the writing data is completed with respect to each of the latch circuits of one page. Therefore, the completion of the latch setting of the writing data in other areas must be waited for in the area where the writing data has already been set, even if the writing operation has been prepared, thereby raising a problem of a loss in the total writing time.
Furthermore, a data latching operation of the next page is not started until the writing operation of one page is completed. Therefore, the completion of the writing operation in other areas must be waited for at an area, where the writing operation has already been completed, even if latching has been prepared for next data, thereby raising a problem of a loss in the writing time for the entire chip.
Moreover, since the writing operation of one page is started in any area at the same time, the writing time is constant all the time, thereby raising a problem that a speed is determined at a writing speed of the slowest memory cell within one page.
SUMMARY OF THE INVENTION
The present invention has been accomplished in an attempt to solve the above problems observed in the prior art. The principal object of the present invention is to provide a semiconductor storage apparatus and a writing method in a semiconductor storage apparatus, in which data writing processing can be performed at a higher speed.
Other objects, features and advantages of the present invention will become clear from the description below.
In order to achieve the above-described object, as a first embodiment for solving the problems, a semiconductor storage apparatus according to the present invention is predicated on a semiconductor storage apparatus, in which data writing latch circuits are connected to bit lines in a memory cell array, a group consisting of the latch circuits and a group consisting of memory cells in columns in the memory cell array are divided into a plurality of areas in a row direction, and the plurality of latch circuits at each of the areas are connected to individual data lines, respectively. In the above-described semiconductor storage apparatus, the plurality of memory cells at each of the areas are commonly connected to individual sub word lines, and further, the sub word line at each of the areas is connected to a main word line via a switching element for a word line.
In other words, it is construed as follows: a semiconductor storage apparatus according to the present invention comprises: a plurality of areas, each of which is divided in a memory cell array in a row direction; a group consisting of memory cells arranged in each of the areas; a group consisting of data writing latch circuits arranged in each of the areas in connection to each of the memory cells in the group consisting of the memory cells via a word line; data lines individually connected to the latch circuits, respectively; sub word lines connected commonly to the group consisting of the memory cells at each of the areas; and a switching element for a word line inserted between each of the sub word lines and the main word line.
Functions of the above-described configuration are as follows: writing data is latched in the group consisting of the latch circuits at a certain one out of the areas divided in the row direction. Upon completion of the data latching, the processing proceeds to data latching with respect to the group consisting of the latch circuits at the other area. In synchronism with this, the switching element for the word line is turned on at the area, at which the data latching has already been completed, and then, the sub word line is connected to the main word line. Thus, an applied potential of the main word line is transmitted to the group consisting of the memory cells at the area via the switching element and the sub word line, and the data is transferred to and written in the group consisting of the memory cells at the area from the group consisting of the latch circuits after the completion of the data latching. In parallel to the writing data latching at one area, the latch data is written in the memory cells at the other area. In other words, it is unnecessary at the area, at which the data latching has been completed, to wait for the completion of the data latching at the other area. Subsequent to the completion of the data latching, the processing proceeds to the data writing without any substantial wait. Consequently, the data writing processing can be efficiently performed at a high speed.
As a second embodiment for solving the problems, a semiconductor storage apparatus according to the present invention is further configured such that a switching element for the latch circuit is interposed between each of the memory cells and each of the latch circuits, the switching elements for the latch circuits are divided per area, and the plurality of
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
Phan Trong
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