Static information storage and retrieval – Read/write circuit – Precharge
Patent
1996-04-16
1998-01-27
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Precharge
3652335, G11C 700
Patent
active
057128243
ABSTRACT:
A semiconductor memory includes a pulse signal generator which receives a clock signal and outputs a first pulse signal and a second pulse signal respectively as a digit line recovery control signal and a word line selection signal. The pulse signal generator includes a first delay circuit and a second delay circuit connected in series, the first delay circuit providing a delay time for a pulse width of the recovery control signal, and the second delay circuit together with the first delay circuit providing a delay time for a pulse width of the word line selection signal. In response to the rising of the clock, the pulse signal generator outputs the digit line recovery control signal and the word line selection signal. Using these signals, digit line recovery is started immediately after cell node inversion during a write operation and word line is rendered non-selected after cell node is stabilized. It is possible to reduce the write cycle time by the extent corresponding to an overlap of the word line selection time and the digit line level recovery time, thus enabling the semiconductor memory to operate fast.
REFERENCES:
patent: 5029135 (1991-07-01), Okubo
patent: 5228003 (1993-07-01), Tokuda
NEC Corporation
Nelms David C.
Tran Michael T.
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