Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1999-11-16
2000-11-28
Utech, Benjamin L.
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
438702, 438713, H01L 21311
Patent
active
061535273
ABSTRACT:
A semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material includes, a) providing a node within a mass of insulating dielectric material; b) first stage etching into the insulating dielectric material over the node in a manner substantially selective relative to the node; c) after the first stage etching, second stage etching the dielectric material in a manner which increases a degree of sidewall polymerization over that occurring in the first stage etching and in a manner substantially selective relative to the node; and d) after the second stage etching, third stage etching the dielectric material with a degree of sidewall polymerization which is less than that of the second stage etching and in a manner substantially selective relative to the first node. An alternate method provides an etch stop annulus cap 70 overlying an electrically conductive ring 62 which projects from a primary insulating layer 54. A secondary insulating 74 is then provided outwardly of the etch stop annulus cap. A second contact opening 76 is patterned and etched through the second insulating layer relative to the first contact opening and to the etch stop annulus cap, with the second contact opening having a wider target area 80 than would otherwise be provided if the annulus cap were not present. Aspects of the invention have significant utility in the fabrication of bit line over capacitor arrays of memory cells.
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Jost Mark E.
Wald Phillip G.
Champagne Donald L.
Micro)n Technology, Inc.
Utech Benjamin L.
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