Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1998-02-23
2000-03-14
Utech, Benjamin
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
438702, 438703, 438713, 438714, H01L 213065
Patent
active
060372613
ABSTRACT:
A semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material includes, a) providing a node within a mass of insulating dielectric material; b) first stage etching into the insulating dielectric material over the node in a manner substantially selective relative to the node; c) after the first stage etching, second stage etching the dielectric material in a manner which increases a degree of sidewall polymerization over that occurring in the first stage etching and in a manner substantially selective relative to the node; and d) after the second stage etching, third stage etching the dielectric material with a degree of sidewall polymerization which is less than that of the second stage etching and in a manner substantially selective relative to the first node. An alternate method provides an etch stop annulus cap overlying an electrically conductive ring which projects from a primary insulating layer. A secondary insulating layer is then provided outwardly of the etch stop annulus cap. A second contact opening is patterned and etched through the second insulating layer relative to the first contact opening and to the etch stop annulus cap, with the second contact opening having a wider target area than would otherwise be provided if the annulus cap were not present. Aspects of the invention have significant utility in the fabrication of bit line over capacitor arrays of memory cells.
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Jost Mark E.
Wald Phillip G.
Champagne Donald L.
Micro)n Technology, Inc.
Utech Benjamin
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