Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-09-05
2006-09-05
Blum, David S. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S254000
Reexamination Certificate
active
07101752
ABSTRACT:
A method for removing defects due to edge chips of a semiconductor wafer is disclosed. This method includes forming a molding layer over a semiconductor wafer. The molding layer is patterned to form a plurality of storage node holes, where the plurality of storage node holes include at least one first storage node hole formed on an effective chip area and at least one second storage node hole formed on an edge chip area. First storage nodes and second storage nodes are formed in the first and second storage node holes, respectively. A photoresist pattern is formed on the wafer having the storage nodes. The photoresist pattern is preferably formed to expose the effective chip areas and to cover the edge chip areas. The molding layer is etched, using the photoresist pattern as an etching mask, to expose portions of the first storage nodes.
REFERENCES:
patent: 2002/0187598 (2002-12-01), Park et al.
Chae Hee-Sun
Park Jeong-Hun
Park Kyoung-Shin
Blum David S.
Marger & Johnson & McCollom, P.C.
LandOfFree
Semiconductor process for removing defects due to edge chips... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor process for removing defects due to edge chips..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor process for removing defects due to edge chips... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3574140