Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-07-07
2001-06-26
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S564000, C438S589000, C438S596000
Reexamination Certificate
active
06251730
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to methods of manufacturing a semiconductor power device having a source region formed using a sidewall extension of an upstanding gate structure, particularly, but not exclusively, comprising a trench-gate. The device may be, for example, an insulated-gate field-effect power transistor (hereinafter termed MOSFET) or an insulated-gate bipolar transistor (hereinafter termed IGBT). The invention also relates to semiconductor devices manufactured by such a method.
In manufacturing a trench-gate power device by a method as disclosed in United States patent specification U.S. Pat. No. 5,378,655 (our reference PHB 33836), an upstanding gate structure is formed at a major surface of a semiconductor body, and a sidewall extension (also termed a “spacer”) is provided at upstanding sides of the gate structure to form a step with an adjacent surface area of a body region of a first conductivity type. The body region of the first conductivity type extends adjacent to the gate structure to provide the device with a channel-accommodating portion, to which the gate is capacitively coupled. In one embodiment, the sidewall extension comprises doped semiconductor material of opposite, second conductivity type which is separated from the gate by insulating material and which provides a source region of the device. The channel-accommodating portion forms a p-n junction with the source region. A source electrode is deposited over the step so as to contact the doped semiconductor material of the sidewall extension and the adjacent surface area of the first conductivity type.
In this method of U.S. Pat. No. 5,378,655 the source region is self-aligned with the trench-gate, by means of the spacers. Two types of embodiment are disclosed. In the first type, the initially-formed spacer is an etchant mask on part of a surface region of the second conductivity type in the body, and exposed areas of the surface region are then etched away to leave a remaining portion of the second conductivity type under the mask as the source region. In the second type, the spacer is of doped material (for example, doped polycrystalline silicon, or a doped oxide or glass) and serves as a dopant diffusion source for diffusing the dopant of the second conductivity type into the semiconductor body to form the source region.
United States patent specification U.S. Pat. No. 5,665,619 discloses a different trench-gate device process in which a spacer (sidewall extension) of insulating material (undoped oxide) is provided on part of a previously-formed source region so as to define a contact window that is self-aligned to the upstanding insulated trench-gate structure. A high-doped portion is then formed in the body by a blanket implant of dopant of the first conductivity type. This high-doped portion has a doping concentration of said first conductivity type which is higher than that of the channel-accommodating portion but lower than the conductivity-determining dopant concentration of the source region. The source region overdopes the ends of the high-doped portion which extends to a shallower depth in the body than the p-n junction between the source region and the channel-accommodating portion of the body region. At the self-aligned contact window, the source electrode contacts the high-doped portion of the body region of the first conductivity type and the adjacent surface area of the source region of the second conductivity type. No such separately-provided high-doped portion of the body region is described in the devices disclosed in U.S. Pat. No. 5,378,655. The whole contents of both U.S. Pat. No. 5,378,655 and U.S. Pat. No. 5,665,619 are hereby incorporated herein as reference material.
SUMMARY OF THE INVENTION
It is an aim of the present invention to provide a method of manufacturing a trench-gate power device which has a source region that is defined by a sidewall extension at the sides of an upstanding insulated trench-gate structure and which has a localised high-doped portion of its body region that is provided, in a self-aligned manner, to a greater depth in the semiconductor body than the p-n junction between the source region and the channel-accommodating portion of the body region.
While forming the localised high-doped portion by dopant introduction, the sidewall extension (comprising the doped semiconductor material of the source region) is used to mask the underlying area of the body where the channel is accommodated. The channel-accommodating portion is protected in this way from the high doping concentration of the localised high-doped portion, so that the channel threshold voltage of the device is not adversely affected. Such a self-aligned process in accordance with the invention readily permits the localised high-doped portion of the first conductivity type to be provided to a greater depth in the semiconductor body than the p-n junction between the source region and the channel-accommodating portion of the body region. This arrangement improves the current flow from deep in the body region to the source electrode. Thereby, the source electrode provides an efficient ohmic contact to the body region, and parasitic bipolar transistor action in the device is reduced, so improving the ruggedness of the device.
The greater depth relationship between the said localised high-doped portion and said p-n junction is achieved by means of the step-up and step-down associated with the source region which comprises the doped semiconductor material of the sidewall extension at the upstanding sides of the gate structure. Thus, the localised high-doped portion of the body region is formed by introducing dopant via the surface area adjacent to the bottom of the step, while using this step (the sidewall extension) as a mask that comprises the doped semiconductor material for the source region.
Accordingly, the depth of the locally-provided high-doped portion in the semiconductor body is determined with respect to this adjacent surface area at the step-down level, whereas the thickness of the source region is determined with respect to the step-up level of the doped semiconductor material of the sidewall extension. This permits the realisation of a device with a very shallow depth for the p-n junction between the source region and the channel-accommodating portion, while using doped semiconductor material of high conductivity in the step so as to avoid a high resistance in this shallow source region. It also permits the depth of the channel-accommodating portion of the body region itself to be made shallow. A shallow channel-accommodating portion means that the device can be made with a short channel length and with a low on-resistance.
Furthermore, the method permits the realisation of an even greater depth for the localised high-doped portion of the body region. Thus, by appropriately designing the height of the step in accordance with the invention, the localised high-doped portion may be provided to a greater depth in the semiconductor body than the channel-accommodating portion or even to a greater depth in the semiconductor body than the bottom of a trench-gate, for example. These arrangements permit the breakdown voltage of the device to be determined by avalanche breakdown of a deep p-n junction between this deep localised high-doped portion and the underlying body portion of the second conductivity type, rather than by avalanche breakdown of a p-n junction between the shallow body region and the underlying body portion or by breakdown at a bottom corner of the trench as may otherwise occur with some trench-gate device designs.
REFERENCES:
patent: 5270257 (1993-12-01), SHin
patent: 5300447 (1994-04-01), Anderson
patent: 5324971 (1994-06-01), Notley
patent: 5371024 (1994-12-01), Hieda et al.
patent: 5374571 (1994-12-01), Mukherjee et al.
patent: 5378655 (1995-01-01), Hutchings et al.
patent: 5665619 (1997-09-01), Kwan et al.
patent: 5684319 (1997-11-01), Hebert
patent: 5864167 (1999-01-01), Cutter
Biren Steven R.
Trinh Michael
U.S. Philips Corporation
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