Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
1999-09-17
2003-03-18
Cuneo, Kamand (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S786000, C257S738000
Reexamination Certificate
active
06534875
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor part for component mounting, a mounting structure and a mounting method.
2. Description of Related Art
Strong demands have been made in recent years for portable electronic equipment such as digital cameras, digital portable telephones and notebook type personal computers that are thinner, are more compact and have lighter weight. Therefore, to what extent the surface mounting density of the semiconductor components used in the above devices can be increased has become an important technical issue.
To cope with this trend, the development of compact CSP (chip scale packages) typified by packaged ICs such as QFPs has progressed and some compact chip scale packages are now available.
These chip scale packages (CSP) incidentally, as can be seen from their other name of FP-BGA (Fine Pitch BGA) are designed for a compact BGA (Ball Grid Array) and their connection pin (hereafter called area terminals) array usually have an 0.8 mm pitch (BGA pitch is 1.27 mm.).
However, to cope with semiconductor LSI chips having higher density and more functions, the scope of the area terminal layout has shown a tend to continually increase and even the size of supposedly small CSP (chip scale packages) are becoming larger.
In order to allow these semiconductor LSI chips to handle a higher component mounting density by accommodating more pins, an even finer pitch is required in the area terminal array.
A chart of semiconductor assembly technology and mounting technology progress accompanying the miniaturization of semiconductor LSI devices is shown in Table 1 below. As can be seen, the number of area terminals has drastically increased to keep pace with higher density, systemization and miniaturization of semiconductor LSI devices. Table 1 also shows that in response to these developments, the CSP and BGA array pitch has become smaller and smaller.
TABLE 1
Development Chart Reflecting Advances in
Semiconductor Technology
Number of
connection
pins
Aluminum
CSP
BGA
Design
(general
electrode
terminal
terminal
Year
scale
purpose)
pitch
pitch
pitch
1997
0.25 &mgr;m
100-295
80 &mgr;m
500 &mgr;m
1.27 &mgr;m
1999
0.18 &mgr;m
117-400
70 &mgr;m
400 &mgr;m
1.27 &mgr;m
2001
0.15 &mgr;m
137-469
60 &mgr;m
400 &mgr;m
1.00 &mgr;m
2003
0.13 &mgr;m
161-551
50 &mgr;m
300 &mgr;m
1.00 &mgr;m
2006
0.10 &mgr;m
205-699
50 &mgr;m
300 &mgr;m
0.80 &mgr;m
In a more specific description given while referring to the drawings, the CSP area terminals 1 and 2 are shown respectively in
FIGS. 5A and 5B
. A 0.8 mm pitch array is shown in
FIG. 5A and a
0.5 mm pitch array is shown in FIG.
5
B. In these figures, the reference numeral
20
denotes the (LSI) chip,
21
denotes a bonding wire,
22
denotes the plastic mold, and
23
denotes the bonding agent (adhesive).
Upon comparing these two pitch arrays in
FIG. 5A and 5B
, it can be clearly observed that as the package size becomes smaller due to miniaturization, the diameter of the area terminal
2
becomes extremely small when the terminal array has a 0.5 mm pitch as shown in FIG.
5
B.
FIG. 6
is a graph showing the correlation of package size and number of area terminal pins for each type of CSP used in portable telephones and handy digital video cameras on the market up till now. The graph shows package size increasing due to the trend to use a greater number of pins, and the package size shrinking from miniaturization with a 0.5 mm pitch array. In other words, the graph clearly shows that high density mounting is indispensable.
However, when miniaturizing the pitch array of area terminals in this way, reducing the size of the terminals is of course unavoidable. Even when mounting (connecting) chip scale packages (CSP) on boards, there is a large possibility of the connection strength deteriorating due to factors such as heat stress after mounting.
On the other hand,
FIG. 7A
shows the area terminals
1
arrayed with an 0.8 mm pitch on a CSP and at a 0.5 mm pitch in
FIG. 7B
along with the repositioned wiring
3
and
3
a
. As this figure clearly shows, more wiring is passing towards the inner side between the area terminals
1
a
and
1
a
rather than on the outermost side.
When the diameter of the area terminals of the 0.8 mm pitch array have for example been set to 0.4 mm, the L/S (line & space) for each wire is 30.8 &mgr;m (wiring pitch of 61.5 &mgr;m). However when the area terminal array is at a 0.5 mm pitch, and the diameter of the area terminals becomes an even smaller 0.25 mm, the wiring between those terminals have an L/S of 19.2 &mgr;m (wire pitch is 38.5 &mgr;m) so that obviously even finer wiring required.
Thus, when many wires are laid between the area terminals and the gap between the terminals becomes exceedingly small, then fine complex processing also becomes necessary on the board. For instance, use of built-up multilayer wiring board such as in the multilayering to rout the wiring
5
to the land terminal
4
is required as shown in
FIGS. 8A and 8B
.
SUMMARY OF THE INVENTION
In view of the above problems with the conventional art, and in view of recent trends toward high density component mounting and increasing the number of pins, this invention therefore has the object of providing a semiconductor part for component mounting, a mounting structure and a mounting method wherein the connection to the printed circuit board is strong and the wiring pitch between terminals has a sufficient width margin.
To achieve the above objects of the invention, a semiconductor part for component mounting of the invention, having area terminals on the substrate is characterized in that, of the area terminals that are arrayed on the outer and inner circumferential sides of the substrate, those area terminals on the outer circumferential side are arrayed with a larger pitch and/or diameter than the area terminals on the inner circumferential side.
To still further achieve the above objects, a mounting structure of this invention comprised of a semiconductor part for component mounting having area terminals, and having land terminals arrayed on the outer and inner circumferential sides of the board is characterized in that the land terminals on the outer circumferential side are arrayed with a larger pitch and/or diameter than the land terminals on the inner circumferential side and further characterized in that a conductive bonding solution is applied between the area terminals and land terminals.
In this invention, the area terminals on the substrate or board are comprised of area terminals arrayed on the outer and inner circumferential sides of the substrate or board. However, in the semiconductor part arrayed with outer circumferential area terminals having a larger pitch and/or diameter than the inner circumferential area terminals, the area terminals may also be arranged in a flip chip bump array.
These area terminals may also be installed on the CSP interposer board, or may be installed on the BGA (ball grid array) or the LGA (land grid array) interposer boards or may be installed on the MCM (multi chip module) subboard.
The area terminals of the semiconductor part of this invention possess a diameter large enough to allow positioning on the outer circumferential side of the board or substrate which is subject to the greatest heat stress, and the strong connection is both stable and reliable so that the connection is more than sufficient to withstand the heat stress applied after mounting.
The pitch array becomes finer (smaller) the more the area terminal is positioned on the inner side away from the outer circumferential side so that the number of terminals can be increased and the board is able to cope with recent and future trends towards increased numbers of pins.
The larger pitch array of the area terminals close to the outer circumference further signifies that the wiring routed between those area terminals towards the inner circumferential terminals has an ample margin and that easier mounting and lower board wiring costs can be achieved. The larger pitch ar
Cruz Lourdes
Cuneo Kamand
Sonnenschein Nath & Rosenthal
Sony Corporation
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