Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2002-03-27
2003-01-21
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S786000, C257S781000, C438S018000, C438S613000
Reexamination Certificate
active
06509582
ABSTRACT:
FIELD OF INVENTION
This invention relates to power semiconductor fabrication, and more specifically to the incorporation of test probing of power semiconductor devices in the fabrication process.
DISCUSSION OF PRIOR ART
Rectangular semiconductor pads usually provide both a location to place a probe and a site for making electrical connections to the package or to other components of a system. For wire bonding packaging, although improper probing can create difficulties, no systematic problems exist that prohibit the use of probes to determine whether a device will meet specifications before expensive continued processing and packaging.
For bump connections, however, varying surface patterns caused by probing can cause systematic problems. To quote from current practitioners: “Bumping over probed I/O pads can result in solder explosions, enlarged and diminished bumps. It is very difficult to cover severe probe damage with a thin UBM layer using an evaporation or sputtering process. If the pad metal has been smeared to such an extent that the UBM does not completely coat the smeared I/O pad metallurgy (typically, A
1
based) poor plating can occur. An enlarged bump is indicative of voids in the solder.” (This quote was taken from p. 1 of “Flip Chip Production Experience: Some Design, Process, Reliability, and Cost Considerations”, by J. D. Mis, G. A. Rinne, P. A. Deane, and G. M. Adema, MCNC Electronic Technologies Division, Research Triangle Park, N.C.)
A second problem with bumping over I/O pads is that plating chemistry reacts with Al metallization, dissolving it away. Large voids in the solder are a field failure reliability risk.
Thus, probing to determine whether a bump device will meet specifications before expensive future processing is either not possible or very difficult.
The conventional placement of source and gate pads is shown in FIG.
1
. The control gate pad
10
occupies one corner of the entire face
5
of the device. The source pad
20
occupies the rest of the face
5
. When gate contact bumps
12
and source contact bumps
22
are added as shown in
FIG. 2
, a single bump
12
is conventionally placed in the middle of the control gate pad
10
, and multiple bumps
22
are conventionally placed in an array across the entire source pad
20
.
See
FIG. 2
a
for a cross section of the prior art layers. Traditional pad construction consists of a layer or layers
52
of dielectric such as an oxide on a substrate
50
, a layer
54
of polysilicon, a layer
56
of conductive metal, one or more passivation layers
58
, and a layer
57
of under bump metal (UBM) overlapping passivation layers
58
.
Dielectric layer or layers
52
insulates the pad from substrate
50
. Conductive metal
56
provides a low resistance interconnect. Polysilicon layer
54
forms a strong adhesive to both oxide
52
and conductive metal
56
. Where required, passivation layer
58
protects conductive metal
56
on specified areas of the wafer from scratches. UBM layer
57
provides an anchor for the bump metal and contact with conductive metal
56
.
Doped polysilicon layer
54
and conductive metal layer
56
are normally used as a gate material. Polysilicon also serves as part of the device I/O protection circuitry. In the pad area, polysilicon layer
54
and conductive metal layer
56
are in direct electrical contact. To insulate polysilicon layer
54
from conductive metal layer
56
on the device outside of the pad area, a dielectric layer
55
is placed between the two layers. A contact mask defines interconnects between layers
54
and
56
where desired. For pad construction, dielectric layer
55
is usually removed between the metal layer
56
and polysilicon layer
54
to use the excellent adhesive properties of the polysilicon to both metal and dielectric layers.
Probing a wafer to determine its acceptability for operation is usually done after solder bumps have been fabricated over the source and gate pads. Fabricating solder bumps is a difficult and error-prone step. Since conventional probing processes damage the surface and increase the risk of device failure due to such probe damage, probing the device before solder bump fabrication is not conventional practice.
FIG. 2
b
shows the results of an attempt to probe a target area
80
where under bump metal is to be placed and a gate bump is to be fabricated. Probe damage
81
partially penetrates gate metallization
56
, and leaves an irregular raised surface
81
a.
When under bump metal
57
is deposited over surface
81
a,
the surface
57
a
of under bump metal
57
substantially follows the surface irregularity of surface
81
a.
Since probe damage metal is mechanically weaker than the gate metallization, and the surface irregularities contribute to poor adhesion between gate metallization and the overlying conductive layers, the result is increased frequency of failure of bump fabrication processing.
A method of locating a testing area for probe placement may be found in U.S. Pat. No. 5,734,175 (Taniguchi), “Insulated-Gate Semiconductor Device Having a Position Recognizing Pattern Directly on the Gate Contact Area”. The '175 patent forms a visible wiring pattern in the gate contact area for wire bonding, but offers no pattern in the source contact area, and does not address the unique requirements of bump contact technology.
SUMMARY
The invention places a visual pattern of insulating material on a semiconductor wafer to guide visually the placement of test probes in device probe areas. To allow probing before bump fabrication, the invention fabricates a passivation layer over probed areas, and planarizes the passivated probed areas, permitting reliable addition of an acceptable layer of under bump metal over the probed area after probing is completed. A gate bump is then fabricated directly over the probed area. These steps facilitate acceptable :test probing of semiconductor device pads before bump connections are fabricated. The invention's approach eliminates from the bump fabrication process every wafer that fails testing, saving the cost of bumping wafers that will be unusable due to low electrical yield.
REFERENCES:
patent: 4628590 (1986-12-01), Udo et al.
patent: 5466348 (1995-11-01), Holm-Kennedy
patent: 5719448 (1998-02-01), Ichikawa
patent: 5844317 (1998-12-01), Bertolet et al.
patent: 5854513 (1998-12-01), Kim
patent: 5965903 (1999-10-01), Chittipeddi et al.
patent: 5969426 (1999-10-01), Baba et al.
patent: 6204074 (2001-03-01), Bertolet et al.
patent: 6407459 (2002-06-01), Kwon et al.
patent: 6426556 (2002-07-01), Lin
Clark Sheila V.
Fairchild Semiconductor Corporation
Fitzgerald, Esq. Thomas R.
LandOfFree
Semiconductor pad construction enabling pre-bump probing by... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor pad construction enabling pre-bump probing by..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor pad construction enabling pre-bump probing by... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3018127