Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2001-11-14
2003-04-01
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C438S108000
Reexamination Certificate
active
06541870
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor packages, and more particularly, to a semiconductor package having at least two stacked chips.
BACKGROUND OF THE INVENTION
In order to enhance functionality and performance of electronic devices, a semiconductor package incorporated with multiple semiconductor chips is desirably created In exemplification of a semiconductor package accommodated with two stacked chips, the two chips are stacked in a stagger manner that bond pads on a lower chip and bonding wires connected thereto are not interfered by an upper chip disposed on the lower chip. However, in such a chip arrangement, the upper chip is partly in contact with the lower chip, thereby making other part of the upper chip suspended with no support from the lower chip. Therefore, in a wire bonding process, the suspended part of the upper chip tends to crack, and thus wire bonding quality is detrimentally affected.
Accordingly, U.S. Pat. Nos. 5,721,542 and 6,215,193 disclose a semiconductor package
1
with supporting structure made as pillars. As shown in
FIGS. 7 and 8
, the semiconductor package
1
includes a chip carrier
10
mounted with a first chip
11
and a second chip
12
, wherein the second chip
12
is stacked on the first chip
11
in a perpendicular stagger manner. A plurality of pillars
13
are interposed between the chip carrier
10
and the second chip
12
. A plurality of bonding wires
14
,
15
are used to electrically connect the chips
11
,
12
respectively to the chip carrier
10
. And an encapsulant
16
is formed to encapsulate the chips
11
,
12
and the pillars
13
. Such a semiconductor package
1
is therefore characterized in the use of the pillars
13
for providing support to the second chip
12
; this is to help eliminate the foregoing chip cracking problem in a wire bonding process, and thereby maintain the second chip
12
intact in structure during connecting the bonding wires
15
to the second chip
12
. However, there are several drawbacks in fabrication and practical use of forming the pillars
13
as supporting structure, as described in the following.
First, in the case of forming two pillars
13
, after mounting the first chip
11
on the chip carrier
10
by an adhesive (not shown), one of the pillars
13
and then the other pillar
13
are in turn adhered onto the chip carrier
10
by the adhesive. In such a three-step attachment process, a usage amount and thickness of the adhesive are hardly controlled, thereby easily resulting in bad coplanarity between top surfaces of the first chip
11
and the pillars
13
. As such, the second chip
12
disposed on the first chip
11
and the pillars
13
cannot be firmly supported with its planarity being degraded. Such a chip
12
then may be bonded with the bonding wires
15
, while the wire bonding quality is undesirably deteriorated. Moreover, due to the pillars
13
positioned beneath the second chip
12
, during forming the encapsulant
16
, mold flow of an encapsulating compound easily generates turbulence within a narrow gap between the second chip
12
and the chip carrier
10
, thereby resulting in the occurrence of voids and also possibly popcorn effect, which therefore seriously affect product quality. In addition, as mentioned above, the pillars
13
are formed on the chip carrier
10
by the multi-step attachment process; this accordingly increases complexity and costs in fabrication. Therefore, how to provide sufficient support to a chip and assure intactness of chip structure and wire bonding quality, is a critical topic to deliberate.
SUMMARY OF THE INVENTION
A primary objective of the present invention is to provide a semiconductor package with stacked chips, in which chip planarity and wire bonding quality are assured.
Another objective of the invention is to provide a semiconductor package with stacked chips, in which the occurrence of voids is eliminated in mold flow of an encapsulating compound.
Still another objective of the invention is to provide a semiconductor package with stacked chips, in which complexity and costs in fabrication are reduced.
A further objective of the invention is to provide a semiconductor package with stacked chips, in which heat dissipating efficiency is improved.
In according with the foregoing and other objectives, the present invention proposes a semiconductor package with stacked chips, comprising: a chip carrier; at least one first chip having an active surface and an opposing non-active surface, wherein the active surface are formed with a plurality of bond pads thereon, and the non-active surface is attached to the chip carrier; at least one second chip having an active surface and an opposing non-active surface, wherein the active surface are formed with a plurality of bond pads thereon, and the non-active surface is partly attached to the active surface of the first chip in a stagger manner that the bond pads on the first chip are not covered by the second chip; a supporting element having an upper surface and an opposing lower surface, wherein the lower surface is attached to the active surface of the second chip in a manner as not to interfere with arrangement of the bond pads on the second chip, and the supporting element is dimensionally sufficient in surface area to cover part of the second chip where no support is provided by the first chip; a plurality of first bonding wires for electrically connecting the bond pads on the first chip to the chip carrier; a plurality of second bonding wires for electrically connecting the bond pads on the second chip to the chip carrier; and an encapsulant for encapsulating the first and second chips, the supporting element, and the first and second bonding wires.
In the semiconductor package with stacked chips of the invention, since the supporting element is dimensionally sufficient in surface area to cover part of the second chip where no support is provided by the first chip, this therefore enhances bending moment of the second chip. As such, in a wire bonding process for connecting the second bonding wires to the second chip, enhance bending moment of the second chip is capable of maintaining intactness in chip structure without the occurrence of cracks of the second chip, and thus the wire bonding quality can be assured. Moreover, unlike supporting structure of pillars used in the prior art, the supporting element of the invention does not interfere with mold flow of an encapsulating compound used for forming the encapsulant, and thus no turbulence or void occurs in the mold flow, thereby not leading to popcorn effect that may cause serious damage in structure. Furthermore, the deposition of the supporting element on the second chip does not undesirably affect the chip planarity; therefore, a drawback in the prior art of unstable disposition of a second chip due to bad coplanarity between pillars and a first chip can be eliminated. In addition, the supporting element can be formed as a plate that is made of a thermally conductive material such as copper or copper alloy, which therefore can be cost-effectively fabricated by using simple processes.
The supporting element of the invention can be formed on its lower surface with at least one protruding portion, which is positioned outside edge sides of the second chip and does not interfere with the connection between the bond pads on the second chip and the second bonding wires. The protruding portion is used to increase structural strength of the supporting element, thereby making the bending moment of the second chip further enhanced, so as to firmly assure the wire bonding quality and structural intactness for the second chip.
The supporting element can further be made with increase in thickness in a manner that, its upper surface is higher in elevation than wire loop tops of the second bonding wires and exposed to outside of the encapsulant. The supporting element with increased thickness can therefore further enhance the bending moment of the second chip, so as to effectively prevent chip cracking from occurre
Ho Tzong-Da
Hsiao cheng-Hsu
Huang Chien-Ping
Corless Peter F.
Edwards & Angell LLP
Fahmy Wael
Farahani Dana
Jensen Steven M.
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