Semiconductor package with selective underfill and...

Details Semiconductor package with selective underfill and... Semiconductor package with selective underfill and...

2007-01-30

2007-01-30

Potter, Roy Karl (Department: 2822)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S613000

Reexamination Certificate

active

11121847

ABSTRACT:
A method of manufacturing a semiconductor package includes providing a substrate having a plurality of contacts with solder bump contact areas that are unmasked. A plurality of underfill bumps is formed on the plurality of contacts selectively in the solder bump contact areas. A die having a plurality of solder bumps is positioned on the substrate so the plurality of solder bumps is substantially vertically aligned with the plurality of underfill bumps. The plurality of solder bumps is pressed into the plurality of underfill bumps until the plurality of solder bumps contacts the plurality of contacts. The plurality of solder bumps is reflowed. The die, the plurality of solder bumps, and the plurality of contacts are encapsulated to expose a lower surface of the plurality of contacts.

REFERENCES:
patent: 6482680 (2002-11-01), Khor et al.
patent: 6507120 (2003-01-01), Lo et al.
patent: 6577012 (2003-06-01), Greenwood et al.
patent: 6597059 (2003-07-01), McCann et al.
patent: 6661087 (2003-12-01), Wu
patent: 2002/0031902 (2002-03-01), Pendse et al.
patent: 2004/0169275 (2004-09-01), Danvir et al.

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