Semiconductor package with low strain seal

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material

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Details

257710, 257729, H01L 2312

Patent

active

057239053

ABSTRACT:
A semi-conductor packaging structure and a method to reduce the seal strain of the package are disclosed. The structure comprises a cap, substrate, seal and the cap and substrate have a predetermined TCE mismatch. The TCE mismatch between the cap and substrate is predetermined to minimize the seal strain during power-on and power-off use conditions. Preferably, the device has a substrate comprises a ceramic material, a cap with a thermal conductivity of at least about 100 W/m-K. A method of selecting a cap material is disclosed.

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