Semiconductor package with improved size, reliability,...

Details Semiconductor package with improved size, reliability,... Semiconductor package with improved size, reliability,...

2010-07-22

2010-12-28

Zarneke, David A (Department: 2891)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S675000, C257SE23011

Reexamination Certificate

active

07858520

ABSTRACT:
The semiconductor package includes a semiconductor package module with circuit patterns formed on an insulation substrate, at least two semiconductor chips electrically connected to each of the circuit patterns using bumps, and an insulation member filled in any open space in the semiconductor module. A cover plate is formed on the upper portion of the semiconductor package module, and a penetration electrode penetrates the semiconductor package. The penetration electrode is electrically connected to the circuit patterns. The described semiconductor package improves upon important characteristics such as size, reliability, warpage prevention, and heat dissipation.

REFERENCES:
patent: 5877561 (1999-03-01), Kim
patent: 6590291 (2003-07-01), Akagawa
patent: 7514770 (2009-04-01), Chang et al.

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