Semiconductor package with controlled solder bump wetting

Details Semiconductor package with controlled solder bump wetting Semiconductor package with controlled solder bump wetting

2008-04-01

2008-04-01

Le, Thao P. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With bumps on ends of lead fingers to connect to semiconductor

C257S737000, C257S772000

Reexamination Certificate

active

07352055

ABSTRACT:
A semiconductor package includes a substrate having a plurality of lead fingers. A plurality of stud bumps is attached to the plurality of lead fingers. A die having a plurality solder bumps is provided. The plurality of solder bumps is attached to the plurality of stud bumps to form a plurality of electrical connections and provide controlled collapse of the plurality of solder bumps. An encapsulant encapsulates the die, the electrical connections, and the plurality of lead fingers to expose a lower surface of the plurality of lead fingers. The plurality of stud bumps may include a plurality of clusters of stud bumps.

REFERENCES:
patent: 6214642 (2001-04-01), Chen et al.
patent: 6310390 (2001-10-01), Moden
patent: 6482680 (2002-11-01), Khor et al.
patent: 6507120 (2003-01-01), Lo et al.
patent: 6577012 (2003-06-01), Greenwood et al.
patent: 6661087 (2003-12-01), Wu
patent: 6828220 (2004-12-01), Pendse et al.
patent: 6865084 (2005-03-01), Lin et al.
patent: 2004/0072396 (2004-04-01), Tiziani et al.
patent: 2004/0178481 (2004-09-01), Joshi et al.
patent: 2005/0173783 (2005-08-01), Chow et al.
patent: 2006/0012055 (2006-01-01), Foong et al.

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