Semiconductor package with a stacked chip on a leadframe

Details Semiconductor package with a stacked chip on a leadframe Semiconductor package with a stacked chip on a leadframe

1998-10-26

2001-10-23

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

On insulating carrier other than a printed circuit board

C257S670000

Reexamination Certificate

active

06307256

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor package, and more specifically, to a leadframe package with a stacked chip formed thereon.
BACKGROUND OF THE INVENTION
The trend of making package elements towards lighter, thinner, and smaller. The following major three problems are frequently encountered during the formation of the package. The first problem is the reliability of connecting points between the pins and the substrate in the package element minimization procedure; the second one is the testing problem encountered in the package element minimization procedure; and the third one is about the circuit routing on its substrate in the package element minimization procedure.
(1) The reliability problem of connecting points between the package element pins and the substrate:
This problem comes mainly from the fatigue destruction of connecting points. There are three factors which affect the fatigue destruction of connecting points: one is their geometrical shapes, another is the difference between the coefficients of thermal expansion (CTEs) of the materials on both sides of the connecting point, and the other is the distance between the connecting point and the geometrical center. In the respect of geometrical shapes, traditional leadframe type package elements have thin and long pins and, on the pins extending from the package body to the substrate, there is a portion that can be distorted. The thermal stress destruction to the connecting points can be lowered by slightly displacing the pins of this type of elements. But for the BGA type package elements, their electrical transferring members are spherical and therefore there is no such “slightly displacing” mechanism to absorb thermal stress. As to the difference between the CTEs of the materials on both sides of the connecting point, since the spherical pins cannot be slightly displaced to lower thermal stress as do the leadframe pins, this CTE difference becomes an indicator of fatigue destruction for spherical pins. Namely, the more difference there is between the CTEs on both sides of the spherical connecting point, the more easily fatigue destruction will happen. Thus, currently the planting area of BGA packages will mostly prevent from the projection area on the wafer. The reason is that the effective CTE of the direct projection area on the substrate will decrease because of the constrain effect of the wafer and consequently enlarge the CTE difference on both sides. For each kind of CSP, which uses spherical metal as electrical connecting members, the footprint of package elements almost occupies the whole projection area of the wafer so that those connecting members can only be distributed within the projection area. This results in serious fatigue destruction problem for CSP connecting points. Current resolution to this problem is to apply underfill around the spherical pins followed by baking to dry the underfill so as to strengthen its ability against fatigue. Nonetheless, the above mending procedure is not in accord with the standard SMT composition procedure. For ordinary SMT composition factories, in addition to the extra equipment for applying underfill, it will also harm other finished elements owing to the high temperature during the baking and drying procedures. In observation of this, inserting elastomer between the wafer and the soft circuit board conveying stannic balls can eliminate the influence of the wafer on the CTE of the circuit board for the CSP structure of BGA, as shown in FIG.
1
A. Additionally,
FIG. 1B
shows the CSP structure of small outline no lead (SON) by Fujitsu and that of USON by LG (Gold Star). In spite that the connecting pins are of lead structure and the CTE difference on both sides of the connecting points is small, yet the fatigue lifetime of these CSP elements still does not exceed 1000 cycles owing to the lack of “slightly displacing” mechanism at the whole connecting point. The resolution of above issue in accordance with the present invention is to take the traditional geometrical outlook of the lead pins.
(2) The testing problem:
The design of the electricity contact of the test connecting point is according to the connecting pins for traditional test sockets. These test connecting points are like curved reeds. After the BGA elements, which have spherical connecting members, were developed, the curved reed structure at the test connecting points is still feasible because the pitch among pins is large enough. This curved reeds structure has a dowel, which is inserted into the circuit board, on one end and a plate-shape contact cushion on the other. For either connecting pins or spherical pins, there is a size error, which is about ⅔ the side of a contact cushion, at the contact point on the cushion for manufacturers to produce sockets. However, when CSP elements, which also have spherical connecting members, were realized, the pitch among spherical pins is so small that traditional curved reed structure is not suitable for electricity contact connecting points. The connection is achieved by ball-to-hole method. Now, the socket hole usually has the probe or metal filament with conductivity. If the sizes of planting are too different when making CSP, it is possible to cause ill contact or open circuit between the ball and the probe or metal filament in the hole and to affect test results. Moreover, traditional test elements utilize geometrical outlook of package elements to fit the pins and the test contact cushion. Therefore, the size error of the elements determines allowable production error in the fitting between pins and the test contact cushion. (Basically, all objects have their production errors.) While the outlook size of CSP elements is shrunk to about that of the wafer and the production error of spherical pins is under 1 mil, the holes on sockets can hardly be made smaller than 1 mil (0.025 mm). Consequently, CSP elements have difficulty in fitting. The resolution is to utilize traditional contact for lead pins. The outlook size of pins has to comply with the JEDEC standards so that tests can be made by traditional sockets but by otherwise tools. After tests are completed, the lead pins should be cut shorter to make the whole size close to that of wafer.)
(3) The circuit routing problem:
It is inevitable to increase layers or to use technology with higher cost to produce substrates because part of the routing on them needs jumps as a consequence of the smaller and smaller pin pitch of package elements. The resolution of aforesaid problem according to the present invention is to stack wafers in face-to-face or back-to-back methods on leadframes. At the same time, other passive elements can be placed on these wafers and also be stacked on themselves. The routing on conveying substrates will be easier and cheaper via such rerouting on leadframes and wafers.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a leadframe package with stacked chip formed thereon by means of flip chip technology.
A further object of the present invention is to provide a chip scale package.
The present invention includes a leadframe formed on a side rail by supporting bars having a plurality of flexible connecting members formed thereon. One terminal of each inner lead is connected to one end of an outer lead, and the other end of the outer lead is connected on a supporting bar. Protruding portions (or alignment elements) are formed at the periphery area of the regions for forming outer leads. One terminal of the protruding portions are connected to the supporting bars. Each outer lead has a first separating portion, preferably V shape recessed portions, formed thereon for separating the leadframe from the side rail in the first separating procedure. Similarly, each outer lead also has a second separating portion, preferably also V shape recessed portions, formed thereon for separating the inner lead from the outer lead in the second separating procedure. The outer lead area is indented from the surface of the leadframe such th

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