Semiconductor package with a chip on a support plate

Details Semiconductor package with a chip on a support plate Semiconductor package with a chip on a support plate

2009-07-30

2010-11-23

Zarneke, David A (Department: 2891)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

Reexamination Certificate

active

07838417

ABSTRACT:
A semiconductor package includes a support plate made of an electrically non-conducting material. Electrical connection vias are formed outside a chip fixing region provided on the front face of the support plate. Electrical connection wires connect pads on a front of the chip to pads on the front of the support plate associated with the electrical connection vias. The front face of the support plate is further provided with at least one intermediate front layer made of a thermally conducting material extending at least partly below the chip. The rear face of the support plate is provided with at least one rear layer made of a thermally conducting material extending at least partly opposite the front layer. The front and rear layers are connected by vias made of a thermally conducting material that fills through-holes made through the plate.

REFERENCES:
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patent: 5409863 (1995-04-01), Newman
patent: 5583377 (1996-12-01), Higgins, III
patent: 5592025 (1997-01-01), Clark et al.
patent: 5741729 (1998-04-01), Selna
patent: 6191477 (2001-02-01), Hashemi
patent: 6282094 (2001-08-01), Lo et al.
patent: 6521990 (2003-02-01), Roh et al.
patent: 6605353 (2003-08-01), Okada et al.
patent: 6861750 (2005-03-01), Zhao et al.
patent: 7422978 (2008-09-01), Lee
patent: 2002/0185722 (2002-12-01), Zhao et al.
Preliminary French Search Report, FR 0312307, dated May 25, 2004.

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