Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2000-01-25
2001-08-07
Williams, Alexander O (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S676000, C257S675000, C257S692000, C257S684000, C257S796000, C257S712000, C257S696000, C257S693000, C257S698000
Reexamination Certificate
active
06271581
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88119455, filed Nov. 8, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor package structure, and more particularly to a semiconductor package structure having universal lead frame and heat sink.
2. Description of Related Art
In the semiconductor industry, the semiconductor packaging, being the last stage of manufacturing process of integrated circuit products, is used for providing a medium of electrical connection between a chip and a printed circuit board (PCB) or other appropriate devices and is also used to protect the chip. Generally, the integrated circuit is encapsulated in a package, then the package is bonded to the printed circuit board or a substrate.
It is the demand of the market makes the semiconductor industry grow very fast, and the level of integration of integrated circuit is getting higher than ever. Consequently, the number of input/output port is increasing, and the package is heading for developing the one with high density. Therefore, the design and fabrication of a die pad used for mounting the chip while performing packaging, and of a printed circuit board or a substrate such as a circuit carrier for the connection of electronic parts needs to be improved. As the speed of calculating process is getting higher and higher, the power consumed and the heat generated is also getting higher and higher. The heat generated after the chip is packaged is not easy to spread away. The conventional way of heat dissipation is to let the heat dissipate by means of the heat conduction through the molding compound, but the molding compound universally used is not a good thermally conductive material. For all of the above-mentioned reasons, the heat-dissipating effect of heat dissipation method provided by the conventional package is very limited.
FIG. 1A
is a cross-sectional view of a semiconductor package according to the prior art. As shown in
FIG. 1A
, a semiconductor package is constructed on a leaf frame
106
. The package comprises a die pad
102
having a top surface
104
, and a plurality of leads
108
. The leads
108
are attached on the top surface
104
and are disposed at the periphery of the die pad
102
. A chip
100
a
mounted on the top surface
104
of the die pad
102
is electrically connected to the leads
108
by bonding wires
110
a.
As the manufacturing technology of the semiconductor has advanced to 0.18 Micron of wire width or even smaller, there are a lot of breakthrough on increasing the integration. Accordingly, the chip size is diminished, and the electronic products are in the trend of “Light, Thin, Short, and Small”. However, as the chip is shrunk, under the same condition of using the same lead frame, the distance between the chip and the leads of the lead frame will be increased.
Similar to
FIG. 1A
, shown in
FIG. 1B
is a schematic cross-sectional view of the semiconductor according to the prior art when the chip is shrunk. As shown in
FIG. 1B
, a chip
100
b
mounted on the top surface
104
of the die pad
102
is electrically connected to the leads
108
by bonding wires
110
b
. As compare with the package shown in FIG.
1
A, when the chip is shrunk from
100
a
to
100
b
while all the other elements of the package keep the same size and same disposition, the required bonding wires become longer from
100
a
to
100
b
. This is due to the fact that the space between the chip
100
b
and the leads
108
in
FIG. 1B
is larger than the space between the chip
100
a
and the leads
108
in FIG.
1
A. The length increase of bonding wires not only increases the manufacturing cost but also affects the electrical performance of the package. Moreover, the encapsulating process can cause the “Wire Sweep” or even the “Wire Cross” of the relatively long bonding wire that results in unnecessary “Short Circuit”.
However, one way to keep the length of the bonding wires unchanged when the chip is shrunk from
100
a
to
100
b
is to make the leads approach toward the center of the lead frame, in other word, to make the leads relatively longer. Accordingly, the lead frame needs to be redesigned and remanufactured which will result in the increase in manufacturing cost too. In other word, the original lead frame can not be used when the size of the chip is changed (either shrunk or enlarged).
SUMMARY OF THE INVENTION
Therefore, it is the objective of the present invention to provide a semiconductor package structure having universal lead frame and heat sink to accommodate different sizes of the chip. Whenever there is a change in the dimension of the chip, the packaging process can be performed without making any changes in the design and manufacturing of new lead frames, in other word, the original lead frames still hold good. Moreover, the bonding wire electrically collecting the chip and the leads of the lead frame is the shortest one, thereby, it can enhance the electrical performance and the reliability of the overall package. In additions, there is a heat sink in the package that can dissipate the heat generated, and the heat sink is employed to substitute for the die pad for chip mounting. Furthermore, the heat sink can be exposed to directly contact the outside elements to facilitate the package to transfer the heat out, thereby, two kinds of this type of packages are available, i.e., Die Pad Heat Sink (DPH) structures and Exposed Die Pad Heat Sinks (EDPH).
In order to attain the foregoing and other objectives, the present invention provides a semiconductor package structure having universal lead frame and heat sink. The semiconductor package structure comprises a chip, a lead frame, a heat sink, a bonding wire, and a molding compound. The leads of the lead frame approaches toward the center portion of the lead frame in order to adapt to various sizes of the chip. The heat sink is mounted on and connected to the leads of the lead frame, and the periphery of the heat sink overlaps the front end of the leads wherein the dimension of the heat sink is not smaller than the size of the chip. The chip is mounted on the heat sink that is also functioned as die pad. The chip is electrically connected to the leads by a bonding wire that is designed to be the shortest. An “electrically insulative, and thermally conductive” layer is employed for bonding the heat sink to the lead frame. A molding compound is employed to encapsulate the chip, a portion or the whole piece of the heat sink, the leads of the lead frame.
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Huang Chien-Ping
Tseng Wei-Chen
Huang Jiawei
J.C. Patents
Siliconware Precision Industries Co., LTD.
Williams Alexander O
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