Semiconductor package having polymer members configured to...

Details Semiconductor package having polymer members configured to... Semiconductor package having polymer members configured to...

2005-09-13

2005-09-13

Pham, Hoai (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Encapsulated

With specified encapsulant

C257S666000, C257S784000

Reexamination Certificate

active

06943457

ABSTRACT:
A bow resistant semiconductor package includes a semiconductor die, a leadframe and a plastic body. The plastic body includes a molded inner member encapsulating the die, and a molded outer member encapsulating the molded inner member. The inner member rigidities the package, and is dimensioned such that the outer member has substantially equal volumes of molding compound on either side of the leadframe. The equal volumes of molding compound reduce thermo-mechanical stresses generated during cooling of the molding compound, and reduce package bow. With reduced package bow, a planarity of the terminal leads on the package is maintained. Also, stresses on bonded connections between the terminal leads and electrodes on a supporting substrate, such as a printed circuit board or multi chip module substrate are reduced. In an alternate embodiment, the package includes volume equalizing members formed on the leadframe configured to equalize the volumes of molding compound on upper and lower segments of the package body.

REFERENCES:
patent: 3706840 (1972-12-01), Moyle et al.
patent: 3721868 (1973-03-01), Smith, Jr.
patent: 3778685 (1973-12-01), Kennedy
patent: 4026008 (1977-05-01), Drees
patent: 4250347 (1981-02-01), Fierkens
patent: 4540603 (1985-09-01), Hidaka et al.
patent: 4788583 (1988-11-01), Kawahara et al.
patent: 4994411 (1991-02-01), Naito
patent: 5057457 (1991-10-01), Miyahara et al.
patent: 5097317 (1992-03-01), Fujimoto et al.
patent: 5147815 (1992-09-01), Casto
patent: 5157478 (1992-10-01), Ueda et al.
patent: 5197183 (1993-03-01), Chia et al.
patent: 5206794 (1993-04-01), Long
patent: 5291059 (1994-03-01), Ishisuka et al.
patent: 5365107 (1994-11-01), Kuraishi et al.
patent: 5394014 (1995-02-01), Ishikawa et al.
patent: 5437915 (1995-08-01), Nishimura et al.
patent: 5442231 (1995-08-01), Miyamoto et al.
patent: 5619065 (1997-04-01), Kim
patent: 5637915 (1997-06-01), Sato et al.
patent: 5638596 (1997-06-01), McCormick
patent: 5659198 (1997-08-01), Okutomo et al.
patent: 5674785 (1997-10-01), Akram et al.
patent: 5739585 (1998-04-01), Akram et al.
patent: 5750423 (1998-05-01), Ishii
patent: 5767570 (1998-06-01), Rostoker
patent: 5770479 (1998-06-01), Brooks et al.
patent: 5793118 (1998-08-01), Nakajima
patent: 5869355 (1999-02-01), Fukaya
patent: 5920114 (1999-07-01), Beaumont
patent: 5970320 (1999-10-01), Yamasaki et al.
patent: 5970322 (1999-10-01), Ichikawa et al.
patent: 5981315 (1999-11-01), Murakami et al.
patent: 5989940 (1999-11-01), Nakajima
patent: 5998866 (1999-12-01), Ochi et al.
patent: 6025212 (2000-02-01), VanNortwick et al.
patent: 6028368 (2000-02-01), Abe
patent: RE36613 (2000-03-01), Ball
patent: 6043430 (2000-03-01), Chun
patent: 6048755 (2000-04-01), Jiang et al.
patent: 6063139 (2000-05-01), Fukaya
patent: 6068180 (2000-05-01), Test
patent: 6091157 (2000-07-01), Black et al.
patent: 6093958 (2000-07-01), Inaba
patent: 6153924 (2000-11-01), Kinsman
patent: 6229202 (2001-05-01), Corisis
patent: 6258624 (2001-07-01), Corisis
patent: 6271056 (2001-08-01), Farnworth et al.
patent: 6281044 (2001-08-01), VanNortwick
patent: 6700210 (2004-03-01), Smith
Book of Semi Standards 1995, Packaging Volume, Specification Dimensions and Tolerances Used to Manufacture Plastic Molded Small Outline Package Tooling, SEMI 1995 pp. 175-178.
“Analysis of Warpage of LSI package”. Copy Right Nitto Denko, 1999.
Lee Choon Kuan et al. “IC Package Warpage—Prediction and Control”, TI Singapore, MOS Memory Package Development Dept., date unknown.
1994 Dram Data Book, Micron Semiconductor, Inc., Packaging Plastic TSOP, p. 7-19, 1994.

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