Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2007-12-07
2011-10-18
Nguyen, Ha Tran T (Department: 2829)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C257S723000, C257S686000, C257S721000
Reexamination Certificate
active
08039302
ABSTRACT:
A semiconductor package has a first semiconductor die mounted on a substrate. A conductive via is formed through the substrate. A first RDL is formed on a first surface of the substrate in electrical contact with the conductive via and the first semiconductor die. A second RDL is formed on a second surface of the substrate opposite the first surface of the substrate die in electrical contact with the conductive via. A second semiconductor die can be mounted on the substrate and electrically connected to the second RDL. Bonding pads are formed over the first and second surfaces of the substrate in electrical contact with the first and second RDLs, respectively. The bonding pads on opposite surfaces of the substrate are aligned. Solder bumps or bond wires can be formed on the bonding pads. The semiconductor packages can be stacked and electrically connected through the aligned bonding pads.
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patent: 2005/0104181 (2005-05-01), Lee et al.
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Bathan Henry D.
Camacho Zigmund R.
Tay Lionel Chien Hui
Atkins Robert D.
Nguyen Ha Tran T
Patent Law Group
Pathak Shantanu C
STATS ChipPAC Ltd.
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