Semiconductor package and method for manufacturing the same

Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Packaging or treatment of packaged semiconductor

Reexamination Certificate

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C438S067000, C257SE33056, C257SE31124

Reexamination Certificate

active

11074796

ABSTRACT:
A semiconductor package comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an active surface, a back surface opposite to the active surface, an optical component disposed on the active surface, and a plurality of pads disposed on the active surface and electrically connected to the optical component; the pad extension traces are electrically connected to the pads; the via holes are formed through the chip and electrically connected to the pad extension traces; the lid is attached on the active surface of the chip; and the plurality of metal traces are disposed on the back surface of the chip, electrically connected to the plurality of via holes, and defines a plurality of solder pads thereon.

REFERENCES:
patent: 6040235 (2000-03-01), Badchi
patent: 6117707 (2000-09-01), Badchi
patent: 2002/0019069 (2002-02-01), Wada
patent: 2003/0080434 (2003-05-01), Wataya
patent: 2003/0113979 (2003-06-01), Bieck et al.
patent: 2003/0231276 (2003-12-01), Miki et al.
patent: 2004/0075761 (2004-04-01), Maeda et al.
patent: 2004/0229405 (2004-11-01), Prabhu
patent: 2005/0258545 (2005-11-01), Kwon
patent: 2006/0043599 (2006-03-01), Akram et al.

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